Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
310 entries found
Wetten, du bist uns schon einmal begegnet? Ob beim Entsperren des Smartphones, in deinem Auto oder Zuhause: X-FAB steckt überall da, wo die analoge und digitale Welt zusammentreffen. Mikrochips made by X-FAB findest du in Smart Watches, Herzschrittmachern, Industrierobotern, Elektroautos, Herzschrittmachern, und vielem mehr.
Als sogenannte Foundry fertigen wir analog-digitale integrierte Schaltkreise auf Siliziumwafern im Kundenauftrag. Mit circa 100.000 Wafer-Starts pro Monat sind wir mit unseren sechs Standorten auf drei Kontinenten und rund 4.000 MitarbeiterInnen einer der weltweit führenden Spezial-Halbleiterhersteller.
Polysilicon is an integral part of many devices in all CMOS process. Very consistent and accurate electrical performance of such material is a need of those devices used in Circuit Under Pad (CUP) applications. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options i.e. METMID and METTHK on a polysilicon resistor placed under the bond pad. Probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance of a polysilicon resistor which was placed underneath the bond pads.
Use of MIMO and beamforming to increase the radiated power. Challenges:
- Performances: at mmWave frequencies, it is important to minimize loss and locate the front-end components close to the radiating elements.
- Mechanicals: the spacing between phased-array elements (λ/2) becomes too small, 5.3 mm at 28 GHz.
Be aware of the avalanche! Learn how an avalanche photodiode (APD) works and see which devices X-FAB is offering for integration in its modular high voltage XH018 process.
Everybody is talking about single photon avalanche diodes (SPAD) for LiDAR and Time-of-Flight. Do you know what is required to upgrade from an APD to a SPAD? How can a good active quenching circuit be designed?
The webinar will introduce newly-developed APD and SPAD devices. You will be provided with information about the key parameters and learn how to integrate them into X-FAB’s process. X-FAB is offering a reference circuit for active quenching: discover how it works and how it could reduce your time for design.
Have you ever sat in front of your IC layout and asked yourself how you need to place guard rings to mitigate unwanted parasitic effects?
If you take the safe approach you may waste precious layout area which increases the overall footprint of your IC. Just imagine if you could know where peaks of substrate current are in order to effectively predict the parasitic effects for countermeasures. To address this challenge X-FAB has enabled PNAware XSUB – a substrate analysis tool developed by the Swiss EDA software vendor PN Solutions.
In this webinar, we will demonstrate the tool which is enabled by X-FAB's PDK environment using examples from the 180 nm high-voltage technology (XH018).
Adhesive wafer bonding using laminated photosensitive dry-resist offers many advantages and can be used to realize advanced, CMOS integrated, volume manufacturable lab-on-a-chip devices. The relatively low bond temperatures involved allow the wafer-level hybrid integration of a range of substrates, e.g. CMOS wafers with structured MEMS glass wafers. The dry-film polymer acts as the adhesive interlayer and can also be lithographically patterned to form sealed microfluidic fluid channels and chambers after the bonding process.
System in package (SiP): a number of ICs or chips are mounted in a single carrier package. Dies may be arranged horizontally or stacked vertically on a substrate, internally connected by: fine wires that are bonded to the package; flip chip technology, solder bumps are used to join stacked chips together; Vertical connections by Through Silicon Vias (TSV)
Effects of 3D Profiles of Adjacent Trench Areas on Rule-Based Etch Bias Retargeting Accuracy for OPC
The shrinkage of critical lithographic feature size keeps introducing new challenges to the standard rule-based etch bias retargeting of Optical Proximity Corrections (OPC). This motivates the use of model-based instead of conventional rule-based etch bias retargeting. On the other hand, model-based retargeting comes with a substantial increase in run-time and complexity.
Wire bonding is an important process of semiconductor assembly by providing electrical connection between integrated circuit and the external leads of semiconductor package. Wire bonding on none-flat surface is uncommon and less exploration as compare to flat surface bond pad. In certain circumstances, wire bonding is required to conduct on none-flat surface. Bond pad with concave surface is initially designed for solder bumping.