Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
305 entries found
Have you ever sat in front of your IC layout and asked yourself how you need to place guard rings to mitigate unwanted parasitic effects?
If you take the safe approach you may waste precious layout area which increases the overall footprint of your IC. Just imagine if you could know where peaks of substrate current are in order to effectively predict the parasitic effects for countermeasures. To address this challenge X-FAB has enabled PNAware XSUB – a substrate analysis tool developed by the Swiss EDA software vendor PN Solutions.
In this webinar, we will demonstrate the tool which is enabled by X-FAB's PDK environment using examples from the 180 nm high-voltage technology (XH018).
Adhesive wafer bonding using laminated photosensitive dry-resist offers many advantages and can be used to realize advanced, CMOS integrated, volume manufacturable lab-on-a-chip devices. The relatively low bond temperatures involved allow the wafer-level hybrid integration of a range of substrates, e.g. CMOS wafers with structured MEMS glass wafers. The dry-film polymer acts as the adhesive interlayer and can also be lithographically patterned to form sealed microfluidic fluid channels and chambers after the bonding process.
System in package (SiP): a number of ICs or chips are mounted in a single carrier package. Dies may be arranged horizontally or stacked vertically on a substrate, internally connected by: fine wires that are bonded to the package; flip chip technology, solder bumps are used to join stacked chips together; Vertical connections by Through Silicon Vias (TSV)
Wire bonding is an important process of semiconductor assembly by providing electrical connection between integrated circuit and the external leads of semiconductor package. Wire bonding on none-flat surface is uncommon and less exploration as compare to flat surface bond pad. In certain circumstances, wire bonding is required to conduct on none-flat surface. Bond pad with concave surface is initially designed for solder bumping.
Effects of 3D Profiles of Adjacent Trench Areas on Rule-Based Etch Bias Retargeting Accuracy for OPC
The shrinkage of critical lithographic feature size keeps introducing new challenges to the standard rule-based etch bias retargeting of Optical Proximity Corrections (OPC). This motivates the use of model-based instead of conventional rule-based etch bias retargeting. On the other hand, model-based retargeting comes with a substantial increase in run-time and complexity.
Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.
The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.
A Re-design root cause in Smart Power ICs, like motor drivers. Some customers are affected by Re-designs due to unwanted substrate coupling, Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem. Not locally concentrated. AC simplifications do not work.
A frequent Re-design root cause in Smart Power ICs, like motor drivers: parasitic Substrate Couplings. Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem, not locally concentrated, AC simplifications do not work.
Do you know what happens to your IC design once you have taped-out to your foundry?
This webinar will shed some light on the various techniques applied in the process from design submission to mask generation. You will learn about the Data Input Check performed by X-FAB to ensure the best possible fabrication quality and how scribe lane structures are added allowing the monitoring of key process parameters. It will also address how the mask generation flow is optimized for different prototyping scenarios such as Single Layer Masks (SLM) and Multi Layer Masks (MLM). In addition, practical suggestions will be provided on how to bypass the reticle limitations by using stitching for large layouts.
In this webinar, we will showcase the different prototyping services X-FAB offers so that you can make the most of your designs and get it first-time-right.