Abstract—We present in this study a novel way to determine the three-dimensional (3D) temperature field of a Radio Frequency Silicon On Insulator (RF SOI) electronic chip, using several resistance temperature detectors (RTDs) embedded at different locations of the chip. The RTDs are designed and placed at different locations to experimentally obtain the temperature at key locations of the chip enabling the calibration of a multiphysical numerical model that provides the 3D temperature field in the whole chip under operating conditions. The obtained results provide useful insights on the role of different parameters (e.g. used materials properties, heat source power, substrate, boundary conditions, etc.) to engineers interested in the modelling and optimization of heat transport and thermal management of electronic chips for RF applications.

Abstract: Several approaches for close integration of GaN power switches with silicon based CMOS logic are subject of technical evaluations and academic discussions. There is a common motivation for the different integration approaches to position gate driver logic and the power gate as close as possible to reduce parasitics and enhance efficiency. While academic research is and has to be done in all fields further industrial development can only occur within commercially promising areas. Therefore commercial boundary conditions impose economic limits to the usability of the different integration approaches to certain potential approaches. Basic cost estimation models for costs per wafer and costs per chip for different integration approaches are checked with real application driven IC examples.

Abstract—This work reports on the progress of the heterointegration of GaN-HEMTs on CMOS wafers by micro-transferprinting (µTP). 200 V and 600 V class device types are successfully transferred from a GaN-on-Si source wafer to a processed CMOS target wafer. Technologies and process steps of the micro-transferprinting are briefly discussed. Both device types are characterized, before micro-transfer-printing on the original Si substrate, and after micro-transfer-printing on the CMOS wafer. The comparison discloses the impact of the micro-transfer-print process on the electrical performance.

Abstract -- HV integrated lateral IGBTs are investigated as an attractive alternative to MOSFETs in integrated high-voltage (up to 230 V), low-power (5 - 500 mW) converters. A performance comparison of SJ-LIGBTs and SJ-MOSFETs is applied to define the design constraints and, consequently, to implement an optimized one-step power conversion topology with both device types. Measurement results of the topology with SJ-LIGBT show an up to 4.2 % higher efficiency in comparison to the SJ-MOSFET converter at 20.4 % smaller power-switch size.