Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
310 entries found
In this webinar, you will learn about:
- The current state of the art in MEMS product design, including compact modeling, CMOS integration, MEMS PDKs and other innovative MEMS design flow techniques.
- New techniques to accelerate the MEMS design process and reduce silicon learning cycles at the foundry, through re-use of established process steps, stacks and technology platforms.
The design concept of a state of the art 40V to 100V n-channel LDMOS is described in this paper. With aggressively thinner buried oxide (BOX) layer, for the first time, a SOI based power LDMOS has achieved comparable energy capability as Bulk BCD technology.
Approaches for wafer level 3D integration of CMOS and MEMS sensors are described in this paper.
I. What is Micro-Tranfer-Printing?
II. MICROPRINCE - Pilot Line for Micro-Transfer-Printing
III. Optimization of Tether Design and Release Etch
I. Introduction
II. NVM Technology & Design
III. NVM Product Integration & Application
The shift of the threshold voltage (Uth) in high voltage metal-oxide-semiconductor field effect transistors (n-MOSFET) with source and drain regions created by an As-implantation with different implanters was investigated. By analyzing the capacitance-voltage curves recorded in metal-oxide-semiconductor structures with different thicknesses of SiO2 and different shapes we found that the shift of Uth in the n-MOSFETs was correlated with the presence of implantation induced defects in the gate oxide. These defects were stable even after the heat treatments at about 1200 K and they appeared in SiO2 due to different pressures in the implantation chamber and different types of gas.
Tomorrows integrated power electronic systems require more efficient power conversion solutions at lower costs.
Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps.
Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design.
Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material.