The shift of the threshold voltage (Uth) in high voltage metal-oxide-semiconductor field effect transistors (n-MOSFET) with source and drain regions created by an As-implantation with different implanters was investigated. By analyzing the capacitance-voltage curves recorded in metal-oxide-semiconductor structures with different thicknesses of SiO2 and different shapes we found that the shift of Uth in the n-MOSFETs was correlated with the presence of implantation induced defects in the gate oxide. These defects were stable even after the heat treatments at about 1200 K and they appeared in SiO2 due to different pressures in the implantation chamber and different types of gas.

Tomorrows integrated power electronic systems require more efficient power conversion solutions at lower costs.

Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps.

Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material.

Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design.

A tunable optical prism MOEMS based on the deformation of a liquid droplet is presented. An aluminum-nitride membrane is tilted by a novel type of thermo-mechanical actuator. The actuatio nprinciple is based on a thermo-mechanical modulation of the intrinsic stress in aluminum-nitride beams. Based on an analytical model, the key parameters of the actuator are optimized.

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. A Finite Element Analysis (FEA) simulation was done to investigate three different stress conditions i.e. cool down after Chemical Vapor Deposition, the increase, and the decrease in temperature during temperature cycling. The highest stress was realized during the increase in temperature during temperature cycling.

The downscaling in ULSI systems, extended life time requirements, the use under harsh environment conditions and new materials influence the reliability of components in terms of stress related defects, corrosion and radiation more and more.Harsh environment requires reliability goals which can be reached by a more application related reliability specification, by new processes, materials or design approaches. Thermal, electrical and mechanical behavior simulation can facilitate the necessary development work by the determination of the main failure mechanisms, the interaction of mechanisms, the degradation behavior of new materials and design.

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS).

Today’s emerging technologies like photovoltaics, smart grid and electromobility are operating at high voltages which are interesting to be sensed on-chip for further processing.