The technology evolution worsens the stress level of microelectronic applications. The shrinking, higher interconnect stacks, the diversity of functions, higher frequencies and power densities lead to higher stress and more interaction of effects. At package and assembly level the densification of internal interconnections, the combination of RF, digital, analog and power, new materials like lead free solder, more aggressive processes and 3D packages deliver new challenges for reliability performance. Requirements of harsh environment applications, the use of consumer products in cars or challenging mission profiles for automotive applications trigger new considerations about reliability determination and description, higher robustness and resilience. Presently the processes, design rules, reliability tests and specifications fit to standards which base on established degradation models and quality assurance processes. But the existing standards like electromigration and stress migration tests for interconnects do not cover all of the new requirements especially due to mechanical stress and stress related limits.

The downscaling in VLSI systems and the use of new materials requires the development of new test structures and in the case of harsh environment conditions the change of the test conditions to higher applied currents and test temperatures. Furthermore the application in wider operating areas and more challenging mission profiles leads to a concept of highly robust metallization stacks in a metal stack system up to eight levels. These stacks can contain a thick top metallization track for high current or RF application. Looking on the metallization systems of liners and cap materials as well as the current carrying metal themselves the differences in the coefficient of thermal expansion (CTE) of the materials lead to intrinsic tension and can result in fatal delamination of the metallization.

Negative Bias Temperature Instability (NBTI) had become one of the most significant device reliability subject reported in this day and age. Not only does NBTI impose a big impact on circuit functionalities as well as product lifetimes, but also becoming the prominent limiting factor for further CMOS technology scaling. Hence accurate characterization and thorough understanding of NBTI is essential to follow or go beyond the Moore’s Law. Nonetheless the existence of NBTI recovery becomes a huge obstruction to this effort; whereby fast reduction in the degradation of the device parameter occurs after end of electrical stress. Moreover device characterization within the measurement stage further increases the NBTI recovery corresponding to the increase in delay.

Ultrasound solutions are widely used in industrial and medical applications for distance measurements and imaging. A multiplexing switch unit is required to drive a piezoelectric transducer array for imaging by a single ultrasound pulse source. Higher frequencies are required for better image resolution.

The design concept of a state of the art 40V to 100V n-channel LDMOS is described in this paper. With aggressively thinner buried oxide (BOX) layer, for the first time, a SOI based power LDMOS has achieved comparable energy capability as Bulk BCD technology.

Approaches for wafer level 3D integration of CMOS and MEMS sensors are described in this paper.