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The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
305 entries found
A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances
due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents
a PSOI technology platformwith the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET), this technology achieves an ON-state resistance of 1435mmm2, an over 50% improvement comparedwith the
state-of-the-artSOI technologies whilemaintaining competitive reliability.
The thinning of GaN wafers is especially delicate as the stabilizing Silicon is removed from already fragile wafers while applying mechanical stress. Two wafers broke not immediately during grinding but while handling afterwards. Currently, a backside process with thicker GaN wafers is being explored additionally.
Modern medical applications rely on semiconductor technologies to build reliable, accurate and innovative devices. If you want to find out what types of technologies X-FAB provides and for which type of devices they can be used, then watch this webinar session covering the following topics:
- Feature-rich CMOS technologies for personal medical devices
- BCD-on-SOI technology for medical ultrasound probes Optical sensors for medical imaging applications
- Silicon-based microfluidics for next-generation DNA sequencing, liquid biopsy or micro electrode arrays
- Single-Photon Avalanche Diodes (SPAD) for life-science applications
Presenter:
Christine Dufour, Program Manager Microfluidics
Alexander Zimmer, Principal Engineer Process Development
Dr. Ulrich Bretthauer, Marketing Manager Medical
The advent of the Internet-of-Things brings new challenges in circuit design. The presence of circuits and sensors in harsh environments brought the need for methodologies that account for them. Since the beginning of the transistors, the temperature is known for having a significant impact on performance, and even though very low temperature sensitivity circuits have been proposed, no general methodology for designing them exists. This paper proposes an extension of the methodology presented in [15], generalizing the gm/ID technique for designing temperature-aware circuits that can
be used either on measurement data, analytically, or based on simulation models. This model is validated using measurements up to 250°C of X-FAB XT018 transistors and later with a Voltage-Controlled Oscillator circuit design example.
For an IC to function reliably in the long-term, you need to be able to predict how a circuit is going to perform after a significant time in operation. Complementing silicon qualification, aging simulations come in handy to estimate the behavior in advance, to fulfill ISO 26262 requirements with regards to functional safety but also to help debug issues identified after reliability stress.
In this webinar, you will learn about the basics of reliability physics and the typical mechanisms that are responsible for transistor aging. The main influencing factors for device degradation will be described and options for limiting them will be discussed.
The presentation will also cover the flow for performing aging simulations in the Cadence design environment, providing examples that illustrate aging impact on circuits and how aging simulation can be used to uncover it.
In addition, the possibilities and limitations of aging simulation are highlighted and suggestions of usage in the day-to-day work of circuit designers are provided along with an overview of current aging model availability in X-FAB’s 180 nm processes and an outlook on upcoming models.
At X-FAB, we put great emphasis on reliability: all our technology platforms must comply with the tough requirements of the automotive industry, and our embedded NVM are no exception to that.
The whole test process for embedded NVM IP, from Design for Test (DFT) to qualification and production screening must be designed upfront and carefully executed to fulfill the automotive quality requirements.
This presentation provides a first overview and some key examples about the challenges and specific approaches in ensuring best-in-class quality for every single NVM IP from X-FAB and how customers can benefit from it.
Whether you want to get a general overview of X-FAB’s large NVM portfolio, or already know the specific functionality, operating conditions and reliability requirements for your project, X-FAB provides an exhaustive and straightforward way to access relevant information.
This short video introduces the available tools for the quick access to helpful information about X-FAB’s NVM portfolio.
Electronic design depends critically on the quality of the PDK - PDK verification becomes more and more important.
With each semiconductor generation more functionality is integrated
- Potential sources of failures are increasing
PDK verification increases the chance of first time right
- Validates the PDK functionality and integrity
- Improves the PDK quality, guarantee the trustworthiness of design
Easily adopted for all XFAB technologies.
Calculation of effective lifetimes based on mission profiles is necessary. Very complex and a lot of manual work necessary with lifetime data from reliability specification.
Reliability Explorer “RelXplorer”
• models from reliability specification are the basis
• models include same safety margin as specification
• considers degradation mechanisms simultaneously
• calculates effective lifetimes based on Mission Profiles
The pace of development and industrialization of LOC devices has been growing – and will further accelerate. Smart integrated microfluidic systems are a key tool to tackle the future opportunities and challenges of digital healthcare. The COVID-19 pandemic being an enormous catalyst to disseminate digital healthcare. Serving a diversified portfolio and a strong customer base ensure steady growth. Technology standardization is the basis for a scalable business model.
Let´s transform the up coming challenges into opportunities together.