This paper presents a novel 3D EM multi-technology simulation flow applied to the Micro-Transfer Printing (MTP) heterogeneous integration technique between GaN and RF-SOI. A modular approach is proposed which relies on the two technology PDKs, the definition of a Cu-RDL technology and an assembly library. This flow addresses the intricate nature of the conformal RDL between the two technologies. Additionally, it offers a complete traceability, physical verification as well as EM simulation environment. The flow is verified with two MTP demonstrators, a CPW transmission line and a DC-6GHz SPDT switch. A good hardware/model correlation is observed which validate the proposed flow.

The effect of Fluorine implantation after gate poly deposition and ex-situ Nitrogen anneal after thin gate oxide formation on Time-Dependent Dielectric Breakdown (TDDB) and Negative-Bias Temperature Instability (NBTI) improvement were studied in 0.13um Dual Gate Oxide CMOS Technology for 5V CMOSFETs. The TDDB lifetime was increased by about 1 order for 5V n/p-MOSFET by Fluorine implantation. The 5V p-MOSFET NBTI lifetime is increased an order of magnitude by Fluorine implantation and the ex-situ Nitrogen anneal. A reduction in the Flicker noise and interface trap density was observed for the group with Fluorine implantation and Ex-situ Nitrogen anneal followed by Fluorine implantation. This result demonstrates that optimization of Fluorine and Nitrogen within the gate oxide is necessary for reliability improvement of 5V CMOSFETs in 0.13um technology.

Hafnium oxide based ferroelectric memory concepts like the FeFET will become increasingly important. They are good scalable, provide high operation speed, and consume low power. Just recently, an 1T1C FeFET concept with one transistor (1T) and one separated ferroelectric capacitor (1C) was demonstrated. This alternative approach is expected to overcome the drawbacks usually observed for the classic 1T concept like limited endurance, reduced retention, and high device-to-device variability. Electrically, the 1T1C FeFET consists of a series connection of the ferroelectric capacitor and the gate oxide capacitance. To operate at low voltages, a large fraction of the applied voltage must drop across the ferroelectric, which can be archived by optimizing the capacitance ratio. Herein, 1T1C
FeFETs with various capacitance ratios are fabricated and its impact on the electrical performance is discussed. Furthermore, the observed endurance of up to 108 field cycles illustrates the
great potential of the new concept.

Abstract — In semiconductor manufacturing, surface defects on wafers must be classified accurately for better yield management. To manage the increasing chip demand in speed and scale, automatic defect classification (ADC) system has been introduced. Most existing ADC systems utilize machine learning-based algorithms that require manual feature extractions and manual intervention such as human-based classification for accuracy and consistency. These methods are labour-intensive, unreliable, and highly prone to human error. Therefore, by leveraging on deep learning technologies, this paper proposes DLADC - an ADC system using a deep convolutional neural network (CNN) architecture for detecting and classifying semiconductor wafer surface defects. The proposed system takes Scanning Electron Microscope (SEM) images as input and outputs the defect’s class and location. The proposed system also sub-classifies particle-type defects into various sizing groups. Identification of defect types that occurred on wafer surfaces allows for better defect root cause analysis, and the additional information of defect size further serves as an essential indication of the origin of machine failure. The proposed DLADC promotes 2x time saving while achieving an improved accuracy of 93.69% based on experimental results with a real semiconductor defect dataset. Not only does DLADC outperforms the 70% classification performance of trained operators, but it also surpasses the 90% classification performance of industrially pragmatic defect classification.

In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.