Commercial sweet spots for GaN and CMOS integration by Micro-Transfer-Printing

Published: Aug 2021

Abstract: Several approaches for close integration of GaN power switches with silicon based CMOS logic are subject of technical evaluations and academic discussions. There is a common motivation for the different integration approaches to position gate driver logic and the power gate as close as possible to reduce parasitics and enhance efficiency. While academic research is and has to be done in all fields further industrial development can only occur within commercially promising areas. Therefore commercial boundary conditions impose economic limits to the usability of the different integration approaches to certain potential approaches. Basic cost estimation models for costs per wafer and costs per chip for different integration approaches are checked with real application driven IC examples.

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