Layout Optimization of CMOS Interconnects for Heating, Cooling and Improved Stress Distribution

The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.

First simulations which support the development work for optimized interconnect layouts as features to improve the reliability of a circuit were prepared. The evaluations started with the heater development of self-heating test structures for higher metal layers for accelerated reliability tests. It continued with the development of a high robust metal stack. The simulations and the tests at heaters and high robust metallization test structures demonstrated the advantages of such a layout improvement.