PNAware Substrate netlist extraction made for circuit designers

A frequent Re-design root cause in Smart Power ICs, like motor drivers: parasitic Substrate Couplings. Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem, not locally concentrated, AC simplifications do not work.

• Status Quo of Parasitic Extraction at XFAB
• PNAware Tool Evaluation Examples
• Backup – PNAware in the design flow