Substrate Netlist Extraction for First-Time-Right Design – How to Avoid Unwanted Parasitic Effects

Have you ever sat in front of your IC layout and asked yourself how you need to place guard rings to mitigate unwanted parasitic effects?
If you take the safe approach you may waste precious layout area which increases the overall footprint of your IC. Just imagine if you could know where peaks of substrate current are in order to effectively predict the parasitic effects for countermeasures. To address this challenge X-FAB has enabled PNAware XSUB – a substrate analysis tool developed by the Swiss EDA software vendor PN Solutions.

In this webinar, we will demonstrate the tool which is enabled by X-FAB's PDK environment using examples from the 180 nm high-voltage technology (XH018).