GaN and CMOS integration

System in package (SiP): a number of ICs or chips are mounted in a single carrier package. Dies may be arranged horizontally or stacked vertically on a substrate, internally connected by: fine wires that are bonded to the package; flip chip technology, solder bumps are used to join stacked chips together; Vertical connections by Through Silicon Vias (TSV)

SiP contains several chips (processors, memories, opto-electronics) on the same substrate – resulting in functional package unit: (1) No or few external components need to be added to make it work (2) Particularly valuable in space constrained environments like mobile phones (3) reduced complexity of printed circuit board (PCB) (4) Critical yield issue: any single defective chip in the package will result in a total fail (even if everything else works fine)