285 entries
Published: Oct 2017

Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design.


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Published: Sep 2017

A tunable optical prism MOEMS based on the deformation of a liquid droplet is presented. An aluminum-nitride membrane is tilted by a novel type of thermo-mechanical actuator. The actuatio nprinciple is based on a thermo-mechanical modulation of the intrinsic stress in aluminum-nitride beams. Based on an analytical model, the key parameters of the actuator are optimized.


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Published: Sep 2017

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. A Finite Element Analysis (FEA) simulation was done to investigate three different stress conditions i.e. cool down after Chemical Vapor Deposition, the increase, and the decrease in temperature during temperature cycling. The highest stress was realized during the increase in temperature during temperature cycling.


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Published: Sep 2017

The downscaling in ULSI systems, extended life time requirements, the use under harsh environment conditions and new materials influence the reliability of components in terms of stress related defects, corrosion and radiation more and more.Harsh environment requires reliability goals which can be reached by a more application related reliability specification, by new processes, materials or design approaches. Thermal, electrical and mechanical behavior simulation can facilitate the necessary development work by the determination of the main failure mechanisms, the interaction of mechanisms, the degradation behavior of new materials and design.


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Published: Sep 2017

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS).


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Published: Sep 2017

Today’s emerging technologies like photovoltaics, smart grid and electromobility are operating at high voltages which are interesting to be sensed on-chip for further processing.


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Published: Aug 2017

LEDs for luminaires:

  • low cost and high efficiency
  • dynamic (spectral) lighting


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Published: Aug 2017

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Published: Aug 2017

Semiconductor passivation layer cracking is considered critical as it can lead to moisture ingress into the device circuits and cause corrosion. The issue is more acute for high aspect ratio thick top metallization where the stress intensity factor (SIF) is higher.


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Published: Aug 2017

In this two-part series of papers, the goal is to reduce thermal stress impact on thick metal passivation. In Part II (this paper), the relationship between passivation thickness and the thermal stress was established using Response Surface Methodology Design of Experiments (RSM DOe).


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