Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
57 entries found
For an IC to function reliably in the long-term, you need to be able to predict how a circuit is going to perform after a significant time in operation. Complementing silicon qualification, aging simulations come in handy to estimate the behavior in advance, to fulfill ISO 26262 requirements with regards to functional safety but also to help debug issues identified after reliability stress.
In this webinar, you will learn about the basics of reliability physics and the typical mechanisms that are responsible for transistor aging. The main influencing factors for device degradation will be described and options for limiting them will be discussed.
The presentation will also cover the flow for performing aging simulations in the Cadence design environment, providing examples that illustrate aging impact on circuits and how aging simulation can be used to uncover it.
In addition, the possibilities and limitations of aging simulation are highlighted and suggestions of usage in the day-to-day work of circuit designers are provided along with an overview of current aging model availability in X-FAB’s 180 nm processes and an outlook on upcoming models.
Calculation of effective lifetimes based on mission profiles is necessary. Very complex and a lot of manual work necessary with lifetime data from reliability specification.
Reliability Explorer “RelXplorer”
• models from reliability specification are the basis
• models include same safety margin as specification
• considers degradation mechanisms simultaneously
• calculates effective lifetimes based on Mission Profiles
Abstract—We present in this study a novel way to determine the three-dimensional (3D) temperature field of a Radio Frequency Silicon On Insulator (RF SOI) electronic chip, using several resistance temperature detectors (RTDs) embedded at different locations of the chip. The RTDs are designed and placed at different locations to experimentally obtain the temperature at key locations of the chip enabling the calibration of a multiphysical numerical model that provides the 3D temperature field in the whole chip under operating conditions. The obtained results provide useful insights on the role of different parameters (e.g. used materials properties, heat source power, substrate, boundary conditions, etc.) to engineers interested in the modelling and optimization of heat transport and thermal management of electronic chips for RF applications.
Polysilicon is an integral part of many devices in all CMOS process. Very consistent and accurate electrical performance of such material is a need of those devices used in Circuit Under Pad (CUP) applications. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options i.e. METMID and METTHK on a polysilicon resistor placed under the bond pad. Probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance of a polysilicon resistor which was placed underneath the bond pads.
Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.
The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.
A Re-design root cause in Smart Power ICs, like motor drivers. Some customers are affected by Re-designs due to unwanted substrate coupling, Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem. Not locally concentrated. AC simplifications do not work.
A frequent Re-design root cause in Smart Power ICs, like motor drivers: parasitic Substrate Couplings. Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem, not locally concentrated, AC simplifications do not work.
Designs are becoming more complex - More integration of sensors, HV, analog, large digital & NVM on one IC. Time-to-market becomes even more important, as well as cost and best-in-class performance. More-than-Moore processes at 180nm and below provide new advantages and enable new products, but also introduce new challenges.
The optimization of a metal-Schottky source-drain NMOS structure and it’s underlying parasitic lateral BJT has been performed on a 0.18 um feature size BCD power IC process. The metal-Schottky structure is fabricated using an ultra-shallow ion implantation which is capable of modifying the barrier height without the need for introduction of non-standard metal systems into the CMOS fab.