Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
36 entries found
While BCD-on-SOI was traditionally considered a niche technology, it has seen a steep rise in adoption in recent years from all major market segments. The higher SOI substrate cost is more than compensated by the many benefits that come with BCD-on-SOI technologies. X-FAB developed its first BCD-on-SOI technology more than 25 years ago and now offers the most extensive foundry BCD-on-SOI technology portfolio.
Our modular processes combine the benefits of dielectric isolation through buried oxide (BOX) and deep trench isolation (DTI) with a wide range of robust HV CMOS, bipolar and well-matched passive primitive devices. XT018 is our leading 180 nm BCD-on-SOI technology solution supporting automotive AEC-Q100 Grade 0 designs and also satisfying the more stringent automotive reliability requirements which become challenging to deal with in Bulk BCD processes.
Learn more about the benefits of dielectric isolation in BCD-on-SOI technologies like latch-up immunity, voltage scalable isolation and ESD-protection, ease of design for circuits with multiple voltage domains and simpler ways to handle AC-coupling effects.
Presenter:
Tilman Metzger, Technical Marketing Manager High Voltage
Dr. Alexander Hoelke, Senior Member Process Development
Guido Janssen, Principal Engineer Design Support
Modern medical applications rely on semiconductor technologies to build reliable, accurate and innovative devices. If you want to find out what types of technologies X-FAB provides and for which type of devices they can be used, then watch this webinar session covering the following topics:
- Feature-rich CMOS technologies for personal medical devices
- BCD-on-SOI technology for medical ultrasound probes Optical sensors for medical imaging applications
- Silicon-based microfluidics for next-generation DNA sequencing, liquid biopsy or micro electrode arrays
- Single-Photon Avalanche Diodes (SPAD) for life-science applications
Presenter:
Christine Dufour, Program Manager Microfluidics
Alexander Zimmer, Principal Engineer Process Development
Dr. Ulrich Bretthauer, Marketing Manager Medical
For an IC to function reliably in the long-term, you need to be able to predict how a circuit is going to perform after a significant time in operation. Complementing silicon qualification, aging simulations come in handy to estimate the behavior in advance, to fulfill ISO 26262 requirements with regards to functional safety but also to help debug issues identified after reliability stress.
In this webinar, you will learn about the basics of reliability physics and the typical mechanisms that are responsible for transistor aging. The main influencing factors for device degradation will be described and options for limiting them will be discussed.
The presentation will also cover the flow for performing aging simulations in the Cadence design environment, providing examples that illustrate aging impact on circuits and how aging simulation can be used to uncover it.
In addition, the possibilities and limitations of aging simulation are highlighted and suggestions of usage in the day-to-day work of circuit designers are provided along with an overview of current aging model availability in X-FAB’s 180 nm processes and an outlook on upcoming models.
Electronic design depends critically on the quality of the PDK - PDK verification becomes more and more important.
With each semiconductor generation more functionality is integrated
- Potential sources of failures are increasing
PDK verification increases the chance of first time right
- Validates the PDK functionality and integrity
- Improves the PDK quality, guarantee the trustworthiness of design
Easily adopted for all XFAB technologies.
(Webinar is presented in Mandarin)
More complex designs, shorter time to market and less time for engineering – these are the challenges IC designers are facing today. X-FAB will be addressing these topics to assist you in your design process and to support you to achieve First-Time-Right designs.
Polysilicon is an integral part of many devices in all CMOS process. Very consistent and accurate electrical performance of such material is a need of those devices used in Circuit Under Pad (CUP) applications. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options i.e. METMID and METTHK on a polysilicon resistor placed under the bond pad. Probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance of a polysilicon resistor which was placed underneath the bond pads.
Have you ever sat in front of your IC layout and asked yourself how you need to place guard rings to mitigate unwanted parasitic effects?
If you take the safe approach you may waste precious layout area which increases the overall footprint of your IC. Just imagine if you could know where peaks of substrate current are in order to effectively predict the parasitic effects for countermeasures. To address this challenge X-FAB has enabled PNAware XSUB – a substrate analysis tool developed by the Swiss EDA software vendor PN Solutions.
In this webinar, we will demonstrate the tool which is enabled by X-FAB's PDK environment using examples from the 180 nm high-voltage technology (XH018).
Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.
A frequent Re-design root cause in Smart Power ICs, like motor drivers: parasitic Substrate Couplings. Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem, not locally concentrated, AC simplifications do not work.
A Re-design root cause in Smart Power ICs, like motor drivers. Some customers are affected by Re-designs due to unwanted substrate coupling, Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem. Not locally concentrated. AC simplifications do not work.