Abstract - This work presents a CMOS test module for the characterization of random telegraph noise (RTN) that can be integrated into regular scribe lines. The proposed module incorporates a novel low
noise current-mode IAF ADC and a standard I2C digital backend for addressing and reading each DUT. A set of 1024-DUT modules has been integrated in the 0.18µm Modular Mixed-Signal HV CMOS technology from X-FAB (XH018). Preliminary experimental results are presented in terms of RTN patterns, spectra, power distributions, spatial mappings for two NMOS transistor types and sizes. The test module can be used to investigate RTN bias dependencies and, with minimal modifications, to speed up testing through RTN subsampling techniques.

Abstract - An improved 4T-Pixel CMOS-Image-Sensor (CIS) is presented, featuring an UV-Window (UVW), a modified Anti-Reflective-Coating (ARC) and Ultra-Low-Noise (ULN) transistors. These are optimizing key parameters such as UV Quantum-Efficiency (QE) and significantly reducing the Read Out-Noise (RON), supporting high-performance imaging in diverse applications. By use of these new features, it is possible to achieve a QE in the UV-Range of 65% with the low Reflective Index (lowRI) ARC and up to 80% with the UVW as well as a RON reduction of more than 50%. 

Abstract - This work presents a simulation and measurement methodology for modeling the Photon Detection Probability (PDP) of Front-Side Illuminated (FSI) CMOS Single-Photon Avalanche Diodes (SPADs) across the ultraviolet visible (UV–VIS) range, achieving over 40% PDP between 
375 nm and 465 nm with 2 V of excess bias above avalanche breakdown. Accurate PDP predictions across temperatures, voltages, and process variations have been achieved by combining modeled absorption profiles, measured quantum efficiency, and avalanche breakdown simulations without relying on fitting parameters.

Abstract - Ferroelectric Capacitors (FeCAPs) based on HfZrO2 (HZO) are promising building blocks for ferroelectric (FE) Non Volatile Memories (NVM). In this work, we investigate for the first time the deposition of FE HZO on top of epitaxial Cobalt Silicide (CoSi2), a mainstream CMOS material. While no systematic studies exist on this combination, our preliminary results demonstrate HZO crystallization on CoSi2 and suggest pathways to improve FE performance toward that of reference stack TiN/HZO/TiN reported in this study and widely used in the literature.

Abstract — An enhanced drift-diffusion Monte Carlo framework is presented for accurately modeling the photon detection probability (PDP) of front-side illuminated (FSI) single-photon avalanche diodes (SPADs) across the UltraViolet-Visible-Infra-Red (UV–VIS–IR) spectrum. This approach combines wavelength-dependent absorption modeling with measured quantum efficiency (QE) to estimate optical losses, and, unlike existing electric-fieldbased models, computes avalanche triggering probability based on carrier trajectories, capturing the contributions of deep-penetrating photons at longer wavelengths. Experimental validation across a range of temperatures, voltages, device pitches, and fabrication processes demonstrates that PDP prediction errors remain below 5% across the entire UV–VIS–NIR spectrum accurately capturing observed QE–PDP discrepancies. Additionally, PDP values exceeding 67% in the UV–VIS range were achieved for small-pitch devices. This framework provides a robust and scalable simulation tool for predictive SPAD design optimization without parameter fitting.

Abstract - This study presents wafer-level packaging using glass-frit bonding to achieve hermetic sensor encapsulation at 8-inch substrate size, ensuring undisturbed performance of several thousand dies per wafer. The screen-printing process was optimized for a miniaturized generation of a MEMS sensor by adapting layout and process parameters, and introducing further improvements described here. For high-volume industrialization, the process was transferred to a fully automated screen-printing tool after prototyping and achieving a production-ready state of the respective processes. Besides the discussion of technical challenges in developing and optimizing the corresponding screen-printing process, the study represents also a best-practice example for a close collaboration between research and industry.

Abstract - This paper reports on a novel type of self-priming porous fluid ports for microfluidic devices. The capillary wicking behaviour of porous microstructures is exploited to facilitate liquid transfer into microchannels. The fluid ports are manufactured by filling pre-structured access holes in glass with micron-sized Al2O3 powder using the PowderMEMS® process. The porous ports are shown to allow reliable and reproducible transport of applied liquids into microfluidic channels. The described approach improves the robustness of fluid transport from the macroscopic world into the microfluidic domain by preventing the formation of a blocking meniscus by surface tension. 
 

Abstract — Long term microelectronic device reliability is important for crucial applications. There is a high percentage of field reliability failure related to wire bond defects. This pointed out that device reliability and system reliability are significantly affected by wire bond reliability. In the scenario of gold wire bonding on aluminum metallization, Excessive intermetallic compound (IMC) growth is a major reliability concern. IMC growth is contributes by gold and aluminum diffusion process. This is an ageing process that will eventually cause high resistance and open circuit of the product. In this study, aluminum bond pads with various characteristics were carefully evaluated to understand IMC growth behavior. Physical factors such as aluminum layer thickness and grains size are the focus of the study. Gold wire material was fixed during wire bonding for all samples, as well as wire bonding parameter settings. Subsequently after wire bonding, accelerated ageing conditioning was applied to the wire bonded samples. High Temperature Storage Life (HTSL) and Temperature Cycle (TC) are two common accelerated ageing methods for device reliability  assessment. HTSL treatment exposed wire bonded samples with continuous high temperatures for a long duration. Meanwhile, TC treatment conditioned the sample between cold and hot environments. Both ageing methods will accelerate IMC growth of Au-Al bonding. Ball bond cross-sectioning was conducted at various phases of HTSL and TC. SEM images were obtained from cross-sectioned samples for close examination of IMC growth patterns. This is followed by a wire bond shear test to evaluate the integrity of Au-Al bonding. The level of IMC growth influenced by aluminum layer thickness and grain size are highly interested in this study. These two characteristics are determined  by deposition rate and temperature used in wafer fabrication process. In view of this, data obtained from this study is valuable information for bond pad structure design and improvement activity in wafer fabrication process.