The history of a highly reliable non-volatile memory

Whenever we store pictures, videos, and addresses in our mobile phones, or run any game or application from our laptop, or more recently exploit the awesome power of Artificial Intelligence, we are either accessing or recording information stored either inside our own devices or on a server in the cloud. As for the human brain’s memory, non-volatile memories (NVM) are those parts of any electronic device or system where such information about “how to” execute one task is stored, and it must stay unchanged when the device is powered off. 

As we use books to write down our memories, electronic devices use electric fields and currents to write information inside specific storage cells. In most cases, this information is digital, with elementary cells either containing a logic “1” or a “0”, representing the minimum “bit” of information. Any NVM technology must grant the basic operations of programming (writing or erasing) and reading the stored data. When in reading mode, the system is accessing the stored information for executing it or using it for other operations. When in programming mode, the system is either writing the data to our electronic book or partially or totally erasing them for correction, update, or replacement for a different task. 

In the 70s, the ability to erase the NVM memory represented a major leap in the proliferation of electronic devices, enabling swifter systems to accept upgrades for the basic start-up function or adapt their software to new tasks without having to redesign the whole device. Programmable firmware or BIOS enabled the early generation PCs to evolve their functions without requiring a complete replacement of the system’s logic. The first EPROM (Erasable Programmable Read-Only Memories) enabled this approach in the 1970s: they could be programmed electrically and completely erased by using UV light. Erasing was not the simplest operation to be performed, and memory upgrades were still a costly and complex operation. A major turning point was the first introduction of EEPROM (Electrically Erasable PROM) by Intel in 1978. 

This technological approach firstly introduced one specific storage element called the “floating gate,” so successful that it is still a reference today. Some X-FAB EEPROM solutions, to name one, are still efficiently exploiting this concept. In figure 1, we report a simplified schematic of the way that a floating gate works. 

A typical embodiment looks like a transistor, with its control gate (G), source (S), and drain (D) terminals, and a very thin “tunnel” oxide separating the floating element from the substrate. When the control gate voltage is raised above a certain level and the other terminals are kept to ground, electrons from the substrate can experience a quantum effect called Fowler-Nordheim (FN) tunneling, getting enough energy to pass through the tunnel oxide and to become confined inside the floating box. When the voltage on the control gate is removed, the terminal will still experience a permanent, floating voltage depending on the amount of accumulated charge, from which the label “floating gate” comes. It’s worth mentioning that alternative ways exist to get electrons jumping beyond the tunnel oxide. These mechanisms, like hot carrier injection (HCI), to name one, will anyway set some trade-off between the programming speed and the level of stress on the oxide, possibly affecting the cell’s long-term reliability.

When the voltage on the control gate is reversed by a comparable amount, the process can be inverted, pushing the electrons out from the floating gate and back to the channel. This accounts for the erasing process. To read the stored value, several approaches are possible. A typical, widespread successful example is the floating-gate flash bit-cells, where the storage element is a poly-silicon box placed between the gate and the conductive channel of a MOS transistor, as reported in figure 2.

This way, injecting electrons in the floating gate will influence the threshold voltage of the corresponding transistor. For an erased cell, virtually no electrons would be present in the floating gate (FG) and raising the voltage on the control gate (CG) will set a conductive layer between the drain (D) and the source (S) of the transistor. Therefore, the transistor will be set ON, which can be interpreted as “data 0” (or “data 1”, depending on the chosen convention). Reversely, if a sufficient number of electrons is injected in the floating gate, their charge will counter-balance the Gate voltage and keep the transistor in an OFF state, which can be conventionally read as “data 1” (or “data 0). Ultimately, injecting (programming) or pushing out (erasing) electrons in the floating gate will change the resistance of the channel between Source and Drain. This way, each floating gate bit-cell can successfully execute the three basic functions of a nonvolatile memory: read, write (program), and erase.

Although very successful, the floating gate mechanism shows some limitations. One of these is the temperature dependency of the tunneling, which can happen in the two senses: after injecting electrons in a cell to program it, thermal agitation can push some electrons back to the channel, resulting in the node leaking charge over time, making it more sensitive to losing its programmed state. This leakage becomes a major issue for those applications expected to be resilient at higher temperatures, like automotive and high-grade industrial applications. Another factor is writing and erasing floating gate memory cells requiring relatively high voltages to be applied to the transistor gates for a fair tunnel current to occur. Such voltages can exacerbate leaks and oxide wear-out over time (“retention” weakness) or produce unwanted perturbation on the neighboring cells during the program phase (“disturb” weakness). Moreover, from a business perspective, the creation of a “double gate” transistor, as in the case of Flash memories (figure 2), increases complexity, cost, and yield control of the semiconductor process.

SONOS technology, which stands for Silicon-Oxide-Nitride-Oxide-Silicon, is a charge trapping technology firstly conceptualized in the late 1960s and early 1970s, and aiming to applications requiring enhanced reliability, temperature resiliency, and scalability on non-volatile memories. The key idea was leveraging a silicon nitride layer, sandwiched between two silicon dioxide layers as the electron trapping material, as reported in figure 3a. This “ONO” layer is placed on top of the conducting Silicon layer acting as a transistor’s conducting channel, and it is eventually capped by the conducting Poly-silicon transistor gate. The resulting SONOS storage element is assembled in figure 3b.