Abstract—This paper, presents a physically-based matching model that includes mismatch fluctuations in HiSIM_HV MOSFET model. Analytical expressions of the variation associated to the threshold voltage, current factor, and drift region resistor were developed and added to the compact model. The proposed model predicts accurately the mismatch in the drain current over a wide operating range and uses only three model parameters. This was validated through Monte Carlo simulations compared to experimental measurements on several device classes from X-FAB 0.18 um processes. The results of the drain current mismatch, the standard deviation of threshold voltage, and the standard deviation of the current factor are presented here and show good agreement between measurements and simulations.

Abstract —Lateral Schottky barrier diodes were implemented in a thin body RF-SOI platform with CoSi2.  Both n-type and p-type device constructions were explored with various geometries and configurations.  Devices were modeled with TCAD, characterized, and their respective performance assessed.  In a demonstration in the targeted application as a zero bias detector, results of output voltage sensitivity to RF input power levels between –20 to 0dBm at frequencies up to 30 GHz are supportive to achieving mmW integrated circuits. 

Keywords — Schottky barrier diode, integrated, RF-SOI, zero bias detector, mmW

Abstract
This paper provides a concise overview of X-FAB and the power electronics markets, with a specific focus on the wide bandgap semiconductors Silicon Carbide (SiC) and Gallium Nitride (GaN). The potential advantages of using power electronics for achieving carbon neutrality will also be discussed. Additionally, the challenges associated with integrating SiC and GaN into a CMOS manufacturing process will be presented. Finally, the paper concludes by offering an outlook on X-FAB's technology strategy for power electronics.

Abstract—This paper presents the Radio Frequency (RF) circuit design and characterization of a Single Pole Double Throw (SPDT) switch. The switch is realized in a Gallium Nitride (GaN)/RF-SOI heterogeneous technology using “Micro-transferprinting”. The measured insertion loss and isolation are respectively below 0.65 dB and -12.7 dB up to 6 GHz. The large signal characterization using a continuous wave shows a hard breakdown at 36 dBm. On the other hand, the pulsed large signal measurement shows a 1dB input compression point of 48 dBm which meets the targeted value. This result confirms that the hard breakdown in CW is due to heat accumulation in the GaN. To address this issue, a heat evacuation technique for future hardware iteration is proposed. This heat evacuation technique should allow to achieve a CP1 of 48 dBm. And so, fully benefit from the advantages from both GaN and RF-SOI technologies on the same chip. 

Keywords—GaN, RF-SOI, Heterogeneous technology, Switch.

Full physical 3D TCAD are often limited to smaller geometries. As the simulation domain increases in size an emulation approach is often taken with lower accuracy [1]. The 375V partial SOI LDNMOS is a large device with a complex, high aspect ratio, multi-region deep trench isolation (DTI) termination structure combined with the HW diode. Additionally, the device has a multitude of small floating silicon regions and a significant amount of silicon/oxide interfaces, coupled with floating field plates. As such, a complete 3D simulation was impossible. A new methodology of domain decomposition using Silvaco’s Victory 3D TCAD [3] has been introduced. The device is broken down into several elements, small enough to enable usage of Monte Carlo Implantation and physical annealing models. After the process simulation, the elements are then joined and re-meshed for device simulation.

Vertical interconnect access (Via) is an electrical structure designed as a bridge between multi-layers metallization of microelectronic silicon wafer. As a conductive gateway between metal layers, via structure is designated at all possible locations in a device base on integrated circuit (IC) routing requirement. As an effective current passageway, it is very common to have via structure fabricated underneath aluminum bonding pad. In the subsequent process of IC packaging, bond pad will be subjected to thermosonic wire bonding by using gold or copper wire. Certain devices will be subjected to ultrasonic wedge bonding of aluminum wire based on specific application.

Over the past years the semiconductor ecosystem has experienced an ever-increasing demand in wafer level integration and packaging technologies, driven by increased requirements on functionality, performance and efficiency. To support the increasing demand for advanced packaging capabilities X-FAB is offering 3D integration and wafer-level packaging methods to enable solutions for advanced system including analog mixed-signal ASICs, sensors, and MEMS. One particular technology out of this variety is the so called “micro-transfer-printing” (μTP) which enables an integration of small-scale devices – also referred to as chiplets – taken from a source and placed on a target wafer in a massively parallel way by applying an elastomeric stamp. Due to its numerous benefits for instance high throughput, integration of small and thin devices, high placement accuracy and short metallization tracks, μTP is regarded as an auspicious technology to support various System in Package (SiP) solutions. To offer this versatile technology, X-FAB has set-up a μTP pilot line for the development and industrialization of related processes in the MEMS clean room facilities in Erfurt, Germany. One focus of X-FAB is the development of print-ready SOI based CMOS ASICs. Print-ready refers thereby to a state in which the ASIC has been separated from the handle wafer and is solely carried by tether, a mechanical structure that keeps the device in place. The general process flow to make devices “print-ready” involves therefore, the chiplet singulation, the tether formation and the release etch.

This paper presents a novel 3D EM multi-technology simulation flow applied to the Micro-Transfer Printing (MTP) heterogeneous integration technique between GaN and RF-SOI. A modular approach is proposed which relies on the two technology PDKs, the definition of a Cu-RDL technology and an assembly library. This flow addresses the intricate nature of the conformal RDL between the two technologies. Additionally, it offers a complete traceability, physical verification as well as EM simulation environment. The flow is verified with two MTP demonstrators, a CPW transmission line and a DC-6GHz SPDT switch. A good hardware/model correlation is observed which validate the proposed flow.

The effect of Fluorine implantation after gate poly deposition and ex-situ Nitrogen anneal after thin gate oxide formation on Time-Dependent Dielectric Breakdown (TDDB) and Negative-Bias Temperature Instability (NBTI) improvement were studied in 0.13um Dual Gate Oxide CMOS Technology for 5V CMOSFETs. The TDDB lifetime was increased by about 1 order for 5V n/p-MOSFET by Fluorine implantation. The 5V p-MOSFET NBTI lifetime is increased an order of magnitude by Fluorine implantation and the ex-situ Nitrogen anneal. A reduction in the Flicker noise and interface trap density was observed for the group with Fluorine implantation and Ex-situ Nitrogen anneal followed by Fluorine implantation. This result demonstrates that optimization of Fluorine and Nitrogen within the gate oxide is necessary for reliability improvement of 5V CMOSFETs in 0.13um technology.

Hafnium oxide based ferroelectric memory concepts like the FeFET will become increasingly important. They are good scalable, provide high operation speed, and consume low power. Just recently, an 1T1C FeFET concept with one transistor (1T) and one separated ferroelectric capacitor (1C) was demonstrated. This alternative approach is expected to overcome the drawbacks usually observed for the classic 1T concept like limited endurance, reduced retention, and high device-to-device variability. Electrically, the 1T1C FeFET consists of a series connection of the ferroelectric capacitor and the gate oxide capacitance. To operate at low voltages, a large fraction of the applied voltage must drop across the ferroelectric, which can be archived by optimizing the capacitance ratio. Herein, 1T1C
FeFETs with various capacitance ratios are fabricated and its impact on the electrical performance is discussed. Furthermore, the observed endurance of up to 108 field cycles illustrates the
great potential of the new concept.