ResourceXplorer: X-FAB

Find our technical papers, webinars, articles

The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.

18 entries found

A Physically-Based Matching Model for HVMOS Transistors

Published: Oct 2023

Abstract—This paper, presents a physically-based matching model that includes mismatch fluctuations in HiSIM_HV MOSFET model. Analytical expressions of the variation associated to the threshold voltage, current factor, and drift region resistor were developed and added to the compact model. The proposed model predicts accurately the mismatch in the drain current over a wide operating range and uses only three model parameters. This was validated through Monte Carlo simulations compared to experimental measurements on several device classes from X-FAB 0.18 um processes. The results of the drain current mismatch, the standard deviation of threshold voltage, and the standard deviation of the current factor are presented here and show good agreement between measurements and simulations.

Posted in: Paper --- Technical Categories: Modeling, High-Voltage

IC Lifetime Calculation Made Easy – Introducing New RelXplorer Tool for Advanced Reliability Evaluation

Published: Jul 2018

Tired of digging through endless process reliability specification documents? If you are looking for an easier way to calculate the lifetime of your ICs, this webinar is just right for you.
We will introduce and demonstrate a new web application – the RelXplorer - which allows you to calculate lifetimes based on mission profiles. It covers all aspects from lifetime parameters and lifetime plots for MOS transistors, capacitors, dielectrics and interconnects.
During this webinar you will learn about the functions and usage of the RelXplorer tool including a live demo session. Join the webinar and find out how the RelXplorer can help you in achieving high reliability with your next IC design.

Posted in: Webinar Recording --- Technical Categories: Simulation, First-Time-Right, Characterization, Modeling, Reliability

reliability lifetime calculator lifetime

Multispectral CMOS Sensors right from the FAB

Published: Dec 2017

Spectral sensors have been attracting increasing interest for years. Solutions available today are limited in terms of space requirements, costs and/or robustness (automotive qualification) in a way that many application scenarios cannot be addressed well.

Technical Categories: Characterization, Modeling, Sensors, More than Moore

spectral sensors foundry spectral sensitivity plasmonic filter dieletric inteference filter photodiodes XO035 XDH10 XH018 XS018 through silicon via TSV multispectral sensing plasmonic metal filters

Unified noise characterisation technique for CMOS technology

Published: Jun 2017

A standardised approach to characterising low-frequency noise for semiconductor devices is presented in this paper. The purpose of this measurement technique is to easily compare performances of different devices from different technologies in order to develop high-precision low-noise technology.

Posted in: Paper --- Technical Categories: Simulation, First-Time-Right, Characterization, Modeling

noise MOSFET BSIM HiSIM Spice flicker thermal low-frequency noise low noise low-noise

Differences in Reliability Effects for Thick Copper and Thick Aluminum Metallizations

Published: Apr 2017

The use of a thick Copper layer on top of an AlCu-metallization stack instead of common thick Aluminium layer triggers a need for a change in the reliability characterization, the test structure layouts and methods. The failure and degradation mechanisms of thick Copper and Aluminium are partly different for the material as well as for thick and thin metal layers.

Posted in: Paper --- Technical Categories: Simulation, Characterization, Modeling, Reliability

thick copper thick aluminium interconnect test structures reliability characterization AlCu-metallization low on-resistance 3D integration electromigration stress migration test structures highly robust creep effect HiRo wide metal tracks slotted wide thick Cu SWEAT high current pulsed DC stress

First-Time-Right Webinar Series (Part IX): ESD Verification Made Easy - How the ESD Design Checker Tool Enables HBM Robustness Simulation

Published: Jul 2016

Nowadays, achieving Human Body Model (HBM) robustness levels from 2kV up to 8kV is a requirement for nearly every newly-designed IC. Designing ESD-robust analog/mixed-signal devices can be a challenging and often daunting task for designers. ESD simulation of integrated circuits from device level up to full chip level is therefore needed to reach this goal without multiple design iterations.

This webinar will showcase how these challenges can be addressed using X-FAB’s ESD Design Checker tool which enables a “virtual“ ESD test on circuit level at an early design stage, providing a first rough estimation of the ESD robustness of the IC. The tool helps in determining ESD discharge paths and identifying possible ESD weak points, thus enabling designers to reduce design cycle time and to achieve first-time-right functional silicon.

Posted in: Webinar Recording --- Technical Categories: First-Time-Right, ESD, Modeling

ESD cells ESD HV I/O library ESD ESD robustness ESD solutions robustness Human Body Model HBM transmission line pulsing transmission line pulse snap-back Cadence XH018

How to Implement System-Level ESD Protection & Safeguarding Against High Energy ESD Pulses

Published: Feb 2016

Elevated levels of integration combined with growing demands for greater cost effectiveness in electronic system implementations (from automotive right through to consumer applications) are increasing the need for IC electro-static discharge (ESD) robustness at the system level. System level ESD is a concern when any IC pin is directly connected to the “outer world”. These external pins have to be able to withstand high energy ESD pulses or else the system's long term operation could be put at risk.
In the latest of its series of informative webinars, X-FAB will discuss the implementation of ESD protection regarding system-level ESD and high energy ESD pulses. It will cover the difference between component and system-level ESD protection, provide insights on how to apply characterization methods such as the Human Metal Model (HMM) and Long-Duration Transmission Line Pulsing (LD-TLP). The presenter will also share best practices for safeguarding against system-level ESD and high energy ESD pulses

Posted in: Webinar Recording --- Technical Categories: First-Time-Right, ESD, Modeling

0.18µm ESD high voltage ESD protection Human Metal Model HMM Long Duration Transmission Line Pulsing LD-TLP Component Level ESD System Level ESD high energy ESD pulse

A design for highly robust ALCU-W-PLUG-metallization stack

Published: Jan 2016

Mission profiles for semiconductor applications are getting more and more challenging regarding electrical and thermo-mechanical robustness of metallization stacks. Effects, especially in thick metals, were investigated over the last years to find solutions for an improvement regarding both potential stressors.

Posted in: Paper --- Technical Categories: Characterization, Reliability, First-Time-Right, Modeling, More than Moore

layout stress robustness metallization shape electro-migration electromigration high temperature lifetime metal stack interconnect reliability design AlCu-metallization layout implementation complex wiring

First-Time-Right Webinar Series (Part VI): Built-in Quality - Methods & Tools to Make Designs Robust Against Manufacturing Process Variability & Aging in Harsh Environment

Published: Jul 2014

To meet stringent quality requirements like 0 ppm, it's essential to build in robust quality and verify it during product design development. This webinar will review the impact of manufacturing variations and tolerances in semiconductor processes for zero-failure-quality targets. It will introduce countermeasures like six-sigma design practice, design centering, robustness indicator figures (RIF) and statistical reliability modeling. Quality verification and robustness validation concepts will be discussed, as well as selected quality assurance methods that can be applied in the manufacturing chain.

Posted in: Webinar Recording --- Technical Categories: First-Time-Right, Analog, Reliability, Modeling, Automotive

0 ppm first time right first-time right first-time-right robust robust design robustness analog design process variants automotive aging simulation failure analysis Monte Carlo simulation Monte Carlo

First-Time-Right Webinar Series (Part II): Prerequisites for first-time-right success – Modeling and process characterization

Published: Sep 2013

This webinar session focuses on the importance of proper characterization data for successful analog design, and discusses how modeling and process characterization can make life easier for analog design engineers. It covers statistic modeling approaches, model quality assurance and process calibration.

Posted in: Webinar Recording --- Technical Categories: Characterization, Modeling, First-Time-Right, Automotive

characterization device characterization modeling modelling Monte Carlo Monte Carlo simulation reliability temperature characterization STI WPE effect statistical models noise characterization substrate leakage