First-Time-Right Webinar Series (Part IX): ESD Verification Made Easy - How the ESD Design Checker Tool Enables HBM Robustness Simulation
Published: Jul 2016
Nowadays, achieving Human Body Model (HBM) robustness levels from 2kV up to 8kV is a requirement for nearly every newly-designed IC. Designing ESD-robust analog/mixed-signal devices can be a challenging and often daunting task for designers. ESD simulation of integrated circuits from device level up to full chip level is therefore needed to reach this goal without multiple design iterations.This webinar will showcase how these challenges can be addressed using X-FAB’s ESD Design Checker tool which enables a “virtual“ ESD test on circuit level at an early design stage, providing a first rough estimation of the ESD robustness of the IC. The tool helps in determining ESD discharge paths and identifying possible ESD weak points, thus enabling designers to reduce design cycle time and to achieve first-time-right functional silicon.