Abstract — In semiconductor manufacturing, surface defects on wafers must be classified accurately for better yield management. To manage the increasing chip demand in speed and scale, automatic defect classification (ADC) system has been introduced. Most existing ADC systems utilize machine learning-based algorithms that require manual feature extractions and manual intervention such as human-based classification for accuracy and consistency. These methods are labour-intensive, unreliable, and highly prone to human error. Therefore, by leveraging on deep learning technologies, this paper proposes DLADC - an ADC system using a deep convolutional neural network (CNN) architecture for detecting and classifying semiconductor wafer surface defects. The proposed system takes Scanning Electron Microscope (SEM) images as input and outputs the defect’s class and location. The proposed system also sub-classifies particle-type defects into various sizing groups. Identification of defect types that occurred on wafer surfaces allows for better defect root cause analysis, and the additional information of defect size further serves as an essential indication of the origin of machine failure. The proposed DLADC promotes 2x time saving while achieving an improved accuracy of 93.69% based on experimental results with a real semiconductor defect dataset. Not only does DLADC outperforms the 70% classification performance of trained operators, but it also surpasses the 90% classification performance of industrially pragmatic defect classification.

Wire bonding is an important process of semiconductor assembly by providing electrical connection between integrated circuit and the external leads of semiconductor package. Wire bonding on none-flat surface is uncommon and less exploration as compare to flat surface bond pad. In certain circumstances, wire bonding is required to conduct on none-flat surface. Bond pad with concave surface is initially designed for solder bumping. 

Shallow Trench Isolation (STI) is a very critical Chemical Mechanical Polishing (CMP) process that requires an exceptional planarization state and reduction of micro-scratches is highly vital [1-2]. Minimizing defects has been a challenging task in STI CMP in both traditionally fumed silica slurry and advanced colloidal silica slurry process [3-4]. Furthermore, the use of ceria (CeO2) slurry in STI CMP heightens this difficulty as ceria slurry tends to agglomerate exceedingly easily in contrast to fumed silica slurry. Additionally, vulnerability to micro-scratches in polished wafers increase exceptionally when ceria (CeO2) slurry is utilized in STI CMP.

The shift of the threshold voltage (Uth) in high voltage metal-oxide-semiconductor field effect transistors (n-MOSFET) with source and drain regions created by an As-implantation with different implanters was investigated. By analyzing the capacitance-voltage curves recorded in metal-oxide-semiconductor structures with different thicknesses of SiO2 and different shapes we found that the shift of Uth in the n-MOSFETs was correlated with the presence of implantation induced defects in the gate oxide. These defects were stable even after the heat treatments at about 1200 K and they appeared in SiO2 due to different pressures in the implantation chamber and different types of gas.