Abstract — An enhanced drift-diffusion Monte Carlo framework is presented for accurately modeling the photon detection probability (PDP) of front-side illuminated (FSI) single-photon avalanche diodes (SPADs) across the UltraViolet-Visible-Infra-Red (UV–VIS–IR) spectrum. This approach combines wavelength-dependent absorption modeling with measured quantum efficiency (QE) to estimate optical losses, and, unlike existing electric-fieldbased models, computes avalanche triggering probability based on carrier trajectories, capturing the contributions of deep-penetrating photons at longer wavelengths. Experimental validation across a range of temperatures, voltages, device pitches, and fabrication processes demonstrates that PDP prediction errors remain below 5% across the entire UV–VIS–NIR spectrum accurately capturing observed QE–PDP discrepancies. Additionally, PDP values exceeding 67% in the UV–VIS range were achieved for small-pitch devices. This framework provides a robust and scalable simulation tool for predictive SPAD design optimization without parameter fitting.

Abstract - This study presents wafer-level packaging using glass-frit bonding to achieve hermetic sensor encapsulation at 8-inch substrate size, ensuring undisturbed performance of several thousand dies per wafer. The screen-printing process was optimized for a miniaturized generation of a MEMS sensor by adapting layout and process parameters, and introducing further improvements described here. For high-volume industrialization, the process was transferred to a fully automated screen-printing tool after prototyping and achieving a production-ready state of the respective processes. Besides the discussion of technical challenges in developing and optimizing the corresponding screen-printing process, the study represents also a best-practice example for a close collaboration between research and industry.

Abstract - This paper reports on a novel type of self-priming porous fluid ports for microfluidic devices. The capillary wicking behaviour of porous microstructures is exploited to facilitate liquid transfer into microchannels. The fluid ports are manufactured by filling pre-structured access holes in glass with micron-sized Al2O3 powder using the PowderMEMS® process. The porous ports are shown to allow reliable and reproducible transport of applied liquids into microfluidic channels. The described approach improves the robustness of fluid transport from the macroscopic world into the microfluidic domain by preventing the formation of a blocking meniscus by surface tension. 
 

Abstract — Long term microelectronic device reliability is important for crucial applications. There is a high percentage of field reliability failure related to wire bond defects. This pointed out that device reliability and system reliability are significantly affected by wire bond reliability. In the scenario of gold wire bonding on aluminum metallization, Excessive intermetallic compound (IMC) growth is a major reliability concern. IMC growth is contributes by gold and aluminum diffusion process. This is an ageing process that will eventually cause high resistance and open circuit of the product. In this study, aluminum bond pads with various characteristics were carefully evaluated to understand IMC growth behavior. Physical factors such as aluminum layer thickness and grains size are the focus of the study. Gold wire material was fixed during wire bonding for all samples, as well as wire bonding parameter settings. Subsequently after wire bonding, accelerated ageing conditioning was applied to the wire bonded samples. High Temperature Storage Life (HTSL) and Temperature Cycle (TC) are two common accelerated ageing methods for device reliability  assessment. HTSL treatment exposed wire bonded samples with continuous high temperatures for a long duration. Meanwhile, TC treatment conditioned the sample between cold and hot environments. Both ageing methods will accelerate IMC growth of Au-Al bonding. Ball bond cross-sectioning was conducted at various phases of HTSL and TC. SEM images were obtained from cross-sectioned samples for close examination of IMC growth patterns. This is followed by a wire bond shear test to evaluate the integrity of Au-Al bonding. The level of IMC growth influenced by aluminum layer thickness and grain size are highly interested in this study. These two characteristics are determined  by deposition rate and temperature used in wafer fabrication process. In view of this, data obtained from this study is valuable information for bond pad structure design and improvement activity in wafer fabrication process. 

Abstract— Within the past decade, the semiconductor ecosystem has witnessed a steadily growing demand for system and functional integration, driven by rising requirements for performance and efficiency. As monolithic integration based on a System-on-Chip (SoC) approach cannot always meet all functional requirements – or may result in higher development effort, time, and cost – alternative System-in-Package (SiP) concepts and technologies are gaining increased attention. XFAB, as an open foundry supplier, has recognized this trend and accordingly expanded its portfolio to include wafer-level integration techniques and advanced materials such as wafer bonding, through-silicon vias (TSVs), and redistribution layers (RDLs). At the same time, the processing of new materials – such as glass, polymers, noble metals, and compound semiconductors – has been successfully integrated into the CMOS manufacturing environment. Another versatile and novel wafer-level integration technology, known as Micro-Transfer-Printing (MTP) – which uses a viscoelastic stamp for the mass transfer of chiplets at wafer level – has been implemented and continuously developed at X-FAB in recent years. This paper introduces the MTP integration technology and highlights the process development achievements at XFAB within recent years that have enabled its implementation in a fab environment. Special emphasis is placed on print-ready processing for SOI-based CMOS wafers and on the wafer-level integration of III-V semiconductor components onto CMOS and photonic wafers, as established at X-FAB.
 

Abstract — Wafer bonding material systems are an important aspect of hermetically sealing the functional cavities of MEMS devices. Typically, wafer bonding processes are set up  as an integral part of the development of MEMS device  manufacturing technology. This results in an optimal bonding process for a specific application, but requires a lot of effort. In fact, this is one of the reasons why a high number of wafer bonding processes are now available and in use. However, for economic and flexibility reasons, wafer foundries are more interested in well-defined bonding processes. Therefore, in this study, known wafer bonding processes are briefly described and evaluated for use in at least two different MEMS foundry processes, considering a variety of requirements for the applications and the production processes, mainly, but not only, lowest possible bond frame width, vacuum sealing behavior, bonding temperature, material system and their CMOS compatibility along with their process complexity. Under these conditions, Au-Si eutectic bonding was found to be the most suitable material system, with other material system such as AlGe eutectic or Ti-Ti direct bonding as an alternative, which require more development and production effort, while other material systems are found not suitable for high volume manufacturing in foundry applications. Finally, the preferred Au-Si bonding system is discussed in more detail.  

Abstract - A significant aspect of fabricating 3D chip architectures is ensuring proper contact between the different layers of the chip, which often requires removing the underside of isolation layers before filling vias with conductive material. Currently, scanning electron microscopy is the established method for investigating such structures. In this paper, we propose a rapid, non-destructive optical analysis technique for the simultaneous measurement of through-silicon vias (TSV) depths, silicon wafer thickness, and residual oxide thickness. The proposed method utilizes Fourier peak shift analysis (FPSA) of reflectance measurements in the near-infrared (1200 nm—2200 nm) spectral regions. The application of FPSA to representative samples taken from a commercial TSV integration process for MEMS and CMOS fabrication demonstrated good agreement with reference scanning electron microscopy measurements, confirming the feasibility of the method for in-line and in-situ metrology. The results indicate that FPSA has great potential for real-time process monitoring and control during 3D chip manufacturing.