Heterogeneous Integration and Wafer - Level Packaging by Micro-Transfer-Printing

Abstract— Within the past decade, the semiconductor ecosystem has witnessed a steadily growing demand for system and functional integration, driven by rising requirements for performance and efficiency. As monolithic integration based on a System-on-Chip (SoC) approach cannot always meet all functional requirements – or may result in higher development effort, time, and cost – alternative System-in-Package (SiP) concepts and technologies are gaining increased attention. XFAB, as an open foundry supplier, has recognized this trend and accordingly expanded its portfolio to include wafer-level integration techniques and advanced materials such as wafer bonding, through-silicon vias (TSVs), and redistribution layers (RDLs). At the same time, the processing of new materials – such as glass, polymers, noble metals, and compound semiconductors – has been successfully integrated into the CMOS manufacturing environment. Another versatile and novel wafer-level integration technology, known as Micro-Transfer-Printing (MTP) – which uses a viscoelastic stamp for the mass transfer of chiplets at wafer level – has been implemented and continuously developed at X-FAB in recent years. This paper introduces the MTP integration technology and highlights the process development achievements at XFAB within recent years that have enabled its implementation in a fab environment. Special emphasis is placed on print-ready processing for SOI-based CMOS wafers and on the wafer-level integration of III-V semiconductor components onto CMOS and photonic wafers, as established at X-FAB.