Abstract— The hafnium oxide based FeFET has attracted much attention due to its good scalability, high operating speed, and low power consumption. However, the integration of this device into CMOS technologies faces several challenges. Recently, the 1T1C FeFET concept with one transistor (1T) and a separate ferroelectric capacitor (1C) in the BEoL has been introduced. This new approach can be integrated into standard process technologies without significant changes at the transistor level. Herein, various stacks and integration schemes are investigated to optimize the BEoL MFM module. The impact of these stacks on key performance parameters of the BEoL MFM module, the 1T1C single-bit memory cell, and an 8 kbit test array is discussed.

Hafnium oxide based ferroelectric memory concepts like the FeFET will become increasingly important. They are good scalable, provide high operation speed, and consume low power. Just recently, an 1T1C FeFET concept with one transistor (1T) and one separated ferroelectric capacitor (1C) was demonstrated. This alternative approach is expected to overcome the drawbacks usually observed for the classic 1T concept like limited endurance, reduced retention, and high device-to-device variability. Electrically, the 1T1C FeFET consists of a series connection of the ferroelectric capacitor and the gate oxide capacitance. To operate at low voltages, a large fraction of the applied voltage must drop across the ferroelectric, which can be archived by optimizing the capacitance ratio. Herein, 1T1C
FeFETs with various capacitance ratios are fabricated and its impact on the electrical performance is discussed. Furthermore, the observed endurance of up to 108 field cycles illustrates the
great potential of the new concept.

In our work we describe and demonstrate an alternative approach of integrating 1T-1C FeFET having separated transistor (1T) without modifying frontend CMOS technology and an additional gate-coupled ferroelectric (FE) capacitor (1C) embedded in the interconnect layers. Starting from the results of FE capacitor integration and 1T-1C single cell characterization this paper describes realization and results of a fully integrated 8 kbit memory array implementation.