Abstract — In semiconductor manufacturing, surface defects on wafers must be classified accurately for better yield management. To manage the increasing chip demand in speed and scale, automatic defect classification (ADC) system has been introduced. Most existing ADC systems utilize machine learning-based algorithms that require manual feature extractions and manual intervention such as human-based classification for accuracy and consistency. These methods are labour-intensive, unreliable, and highly prone to human error. Therefore, by leveraging on deep learning technologies, this paper proposes DLADC - an ADC system using a deep convolutional neural network (CNN) architecture for detecting and classifying semiconductor wafer surface defects. The proposed system takes Scanning Electron Microscope (SEM) images as input and outputs the defect’s class and location. The proposed system also sub-classifies particle-type defects into various sizing groups. Identification of defect types that occurred on wafer surfaces allows for better defect root cause analysis, and the additional information of defect size further serves as an essential indication of the origin of machine failure. The proposed DLADC promotes 2x time saving while achieving an improved accuracy of 93.69% based on experimental results with a real semiconductor defect dataset. Not only does DLADC outperforms the 70% classification performance of trained operators, but it also surpasses the 90% classification performance of industrially pragmatic defect classification.

Polysilicon is an integral part of many devices in all CMOS process. Very consistent and accurate electrical performance of such material is a need of those devices used in Circuit Under Pad (CUP) applications. This paper presents an investigation on stress impact of probe insertions on two bond pad metal options i.e. METMID and METTHK on a polysilicon resistor placed under the bond pad. Probing results in residual stress on both Back End Of Line (BEOL) as well as Front End Of Line (FEOL) structures. This residual stress would impact the electrical properties of the polysilicon material used in such devices. In this study, such electrical impact is measured in terms of change in resistance of a polysilicon resistor which was placed underneath the bond pads.

Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.