Towards a Vertical Membrane GaN MOSFET Process on 200mm GaN-on-Silicon Wafers: Challenges and Solutions

A commercially attractive vertical GaN MOSFET process using 200 mm GaN-on-Silicon substrate wafers in an industrial CMOS environment.
Main challenges are:

• Epitaxially grown PiNN+ GaN structure
• Frontside MOSFET gate
• Membrane approach, with cavities etched from the backside upwards and sub-sequent thick metallization