Don't Screw Up Your Driver! - Simplified Design of Low-RDSon Drivers by Using Advanced Layout Automation & Verification Flows

Today’s state-of-the-art SOI processes support very compact deep-trench-isolated high-voltage devices with a significantly smaller footprint than is possible with conventional isolation schemes, fulfilling the needs of the growing smart power IC market. While the low RDSon of these devices helps to create very area-efficient drivers, it introduces new challenges to the design of the metal interconnect and the distribution of high current densities.
This webinar will discuss how these challenges can be addressed using the latest design and verification tools. In addition, possibilities for layout automation using a pcell-based driver metallization will be shown. This highly automated layout flow enables designers to quickly evaluate several different layout variants and architectures avoiding error-prone manual layout.