In this two-part series of papers, the goal is to reduce thermal stress impact on thick metal passivation. In Part II (this paper), the relationship between passivation thickness and the thermal stress was established using Response Surface Methodology Design of Experiments (RSM DOe).

Semiconductor passivation layer cracking is considered critical as it can lead to moisture ingress into the device circuits and cause corrosion. The issue is more acute for high aspect ratio thick top metallization where the stress intensity factor (SIF) is higher.

Bond pad quality and reliability evaluation is part of important structure test for wafer fabrication. In order to ensure production consistency, and part of continuous monitoring, as well as new process qualification, bond pad evaluation through wire bond is required. Usually the test was conducted by proceed through standard IC packaging such as wafer saw, die attach and wire bond to simulate actual mass production environment. Optionally this can also be done by using wafer level wire bond. Main advantage of wafer level wire bond is shorter test cycle as compare to conventional package level bonding. This could be a significant time saving especially in the fast pace semiconductor field. Key concern of wafer level bonding is the correlation of bonding performance as compare to real application in the field.

Standard design passivation layers on thick (> 3000 nm) top metalization has a susceptibility for cracking due to thermal stress. In this two part series of papers, Finite Element Analysis (FEA) simulation with Comsol Multiphysics was used to understand the impact of thermal stress. In Part I (this paper), three different thermal stress conditions were investigated i.e. cool down after Chemical Vapor Deposition (CVD), the increase, and the decrease in temperature during temperature cycling.

Sensor interfacing is a crucial component for today’s systems in many application domains. Especially in automotive and manufacturing fields, high temperatures are encountered. For extracting the typically small sensor signals, an interface near the sensor is needed to provide a high-accuracy and robustness.

Crystallized-shaped defect was detected after MIM (Metal-Insulator-Metal) Etch post clean step & the defect was found at the edge of MIM structure. The Energy-dispersive X-ray spectroscopy (EDX) analysis showed that the defect is fluorine contaminant after MIM Etch post cleaning step due to long delayed (>5hours).

This paper focus on optimizing Bosch Deep Trench Isolation (DTI) recipe, in order to eliminate silicon grass formation at Shallow Trench Isolation (STI) topology structure. The effectiveness of each etching parameters optimization towards silicon grass elimination has been studied. Silicon grass was observed at STI topology structure after Octaflurocyclobutane (C4F8) gas was added into etching step.

In view of reducing the process development cycle times with plausible time-to-market goals, it is of great demands to speed up the assessment pace, but at the same time not to jeopardize for the high level of quality requirements. Highly robust designs and process margins are the key differentiators and should be enforced in particular for the automotive markets. In this work, development of the fast wafer-level reliability (FWLR) `pulsed' tests that are performed in a relatively short time span under highly accelerated stress conditions on the standard parametric test station (PCM) is revealed here. This is incredibly useful and saving a lot of time especially for compact DOE analysis.