The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.

By this article an introduction of a highly robust metal track layout especially suitable for high current and temperature applications will be introduced. Starting with the reliability limitations normally observed for wide metal tracks, conclusions regarding the requirements for robust layout techniques will be drawn.

The huge demand for high voltage, high current power devices on Silicon on Chip (SoC) has led to the development of Lateral IGBT (LIGBT), touted as the best candidate to serve these two purposes. This paper is the first to review the research works on LIGBTs published till now. The LIGBTs are categorized into four types based on different technologies applied, mainly Junction Isolation (JI), Silicon On Insulator (SOI), Partial SOI (PSOI) and Membrane, and ten varieties based on their device mechanisms, such as Reverse Conducting, Trench Gate and Super Junction.

This paper presents a simple but effective way to improve an NMOS transistor’s ESD robustness for use in I/O pads. Simulation and physical failure analysis has been performed to identify the source of the ESD failure. Process splits have been performed primarily at LDD (Lightly Doped Drain) implant and salicidation process based on data presented in this paper.

An original work in developing technology that allows the integration of multiple vertical power devices within Power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability.