Abstract —Lateral Schottky barrier diodes were implemented in a thin body RF-SOI platform with CoSi2.  Both n-type and p-type device constructions were explored with various geometries and configurations.  Devices were modeled with TCAD, characterized, and their respective performance assessed.  In a demonstration in the targeted application as a zero bias detector, results of output voltage sensitivity to RF input power levels between –20 to 0dBm at frequencies up to 30 GHz are supportive to achieving mmW integrated circuits. 

Keywords — Schottky barrier diode, integrated, RF-SOI, zero bias detector, mmW

Full physical 3D TCAD are often limited to smaller geometries. As the simulation domain increases in size an emulation approach is often taken with lower accuracy [1]. The 375V partial SOI LDNMOS is a large device with a complex, high aspect ratio, multi-region deep trench isolation (DTI) termination structure combined with the HW diode. Additionally, the device has a multitude of small floating silicon regions and a significant amount of silicon/oxide interfaces, coupled with floating field plates. As such, a complete 3D simulation was impossible. A new methodology of domain decomposition using Silvaco’s Victory 3D TCAD [3] has been introduced. The device is broken down into several elements, small enough to enable usage of Monte Carlo Implantation and physical annealing models. After the process simulation, the elements are then joined and re-meshed for device simulation.

A partial silicon on insulator (PSOI) is a widely recognized technology suitable for high-voltage (HV) architectures for power integrated circuits (PICs). Despite the added process complexity compared with SOI reduced surface field (RESURF), this technology offers a wider range of voltage ratings due to the action of the depletion layer in the handle wafer (HW), reduced parasitic capacitances
due to the extra volume of the depletion region in the HW, and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-D designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of HV integrated circuits (HVICs) where low ON-state resistance and reduced self-heating are essential requirements. This work presents
a PSOI technology platformwith the voltage ratings ranging from 45 to 400 V while providing low ON-state resistance, good hot carrier injection stability, as well as electrostatic discharge (ESD) capability of the HV devices. For example, for a 375-V rated laterally diffused MOSFET (LDMOSFET), this technology achieves an ON-state resistance of 1435mmm2, an over 50% improvement comparedwith the
state-of-the-artSOI technologies whilemaintaining competitive reliability.

Abstract—We present in this study a novel way to determine the three-dimensional (3D) temperature field of a Radio Frequency Silicon On Insulator (RF SOI) electronic chip, using several resistance temperature detectors (RTDs) embedded at different locations of the chip. The RTDs are designed and placed at different locations to experimentally obtain the temperature at key locations of the chip enabling the calibration of a multiphysical numerical model that provides the 3D temperature field in the whole chip under operating conditions. The obtained results provide useful insights on the role of different parameters (e.g. used materials properties, heat source power, substrate, boundary conditions, etc.) to engineers interested in the modelling and optimization of heat transport and thermal management of electronic chips for RF applications.

Abstract -- HV integrated lateral IGBTs are investigated as an attractive alternative to MOSFETs in integrated high-voltage (up to 230 V), low-power (5 - 500 mW) converters. A performance comparison of SJ-LIGBTs and SJ-MOSFETs is applied to define the design constraints and, consequently, to implement an optimized one-step power conversion topology with both device types. Measurement results of the topology with SJ-LIGBT show an up to 4.2 % higher efficiency in comparison to the SJ-MOSFET converter at 20.4 % smaller power-switch size.

The design concept of a state of the art 40V to 100V n-channel LDMOS is described in this paper. With aggressively thinner buried oxide (BOX) layer, for the first time, a SOI based power LDMOS has achieved comparable energy capability as Bulk BCD technology.

The advantages of silicon-on-insulator (SOI) technology are reduced parasitic device capacitance, improved performance as well as smaller build area. Despite the gains of SOI technology to manufacturers, new challenges arise in Physical Failure Analysis (PFA). The process of delayering polysilicon or active layer becomes impossible without harming the top silicon. This study discussed the challenges of the current fastest, reliable and reproducible method to delayer polysilicon and divulge active layer. Current delayering method using 49% Hydrofluoric (HF) concentration and SC1 solution is proven to be a faster way to reveal polysilicon layer for Bulk Commentary Metal-Oxide Semiconductor (Bulk CMOS).

Sensor interfacing is a crucial component for today’s systems in many application domains. Especially in automotive and manufacturing fields, high temperatures are encountered. For extracting the typically small sensor signals, an interface near the sensor is needed to provide a high-accuracy and robustness.