Vertical interconnect access (Via) is an electrical structure designed as a bridge between multi-layers metallization of microelectronic silicon wafer. As a conductive gateway between metal layers, via structure is designated at all possible locations in a device base on integrated circuit (IC) routing requirement. As an effective current passageway, it is very common to have via structure fabricated underneath aluminum bonding pad. In the subsequent process of IC packaging, bond pad will be subjected to thermosonic wire bonding by using gold or copper wire. Certain devices will be subjected to ultrasonic wedge bonding of aluminum wire based on specific application.

Abstract — In semiconductor manufacturing, surface defects on wafers must be classified accurately for better yield management. To manage the increasing chip demand in speed and scale, automatic defect classification (ADC) system has been introduced. Most existing ADC systems utilize machine learning-based algorithms that require manual feature extractions and manual intervention such as human-based classification for accuracy and consistency. These methods are labour-intensive, unreliable, and highly prone to human error. Therefore, by leveraging on deep learning technologies, this paper proposes DLADC - an ADC system using a deep convolutional neural network (CNN) architecture for detecting and classifying semiconductor wafer surface defects. The proposed system takes Scanning Electron Microscope (SEM) images as input and outputs the defect’s class and location. The proposed system also sub-classifies particle-type defects into various sizing groups. Identification of defect types that occurred on wafer surfaces allows for better defect root cause analysis, and the additional information of defect size further serves as an essential indication of the origin of machine failure. The proposed DLADC promotes 2x time saving while achieving an improved accuracy of 93.69% based on experimental results with a real semiconductor defect dataset. Not only does DLADC outperforms the 70% classification performance of trained operators, but it also surpasses the 90% classification performance of industrially pragmatic defect classification.

Wire bonding is an important process of semiconductor assembly by providing electrical connection between integrated circuit and the external leads of semiconductor package. Wire bonding on none-flat surface is uncommon and less exploration as compare to flat surface bond pad. In certain circumstances, wire bonding is required to conduct on none-flat surface. Bond pad with concave surface is initially designed for solder bumping. 

Shallow Trench Isolation (STI) is a very critical Chemical Mechanical Polishing (CMP) process that requires an exceptional planarization state and reduction of micro-scratches is highly vital [1-2]. Minimizing defects has been a challenging task in STI CMP in both traditionally fumed silica slurry and advanced colloidal silica slurry process [3-4]. Furthermore, the use of ceria (CeO2) slurry in STI CMP heightens this difficulty as ceria slurry tends to agglomerate exceedingly easily in contrast to fumed silica slurry. Additionally, vulnerability to micro-scratches in polished wafers increase exceptionally when ceria (CeO2) slurry is utilized in STI CMP.

The downscaling in VLSI systems and the use of new materials requires the development of new test structures and in the case of harsh environment conditions the change of the test conditions to higher applied currents and test temperatures. Furthermore the application in wider operating areas and more challenging mission profiles leads to a concept of highly robust metallization stacks in a metal stack system up to eight levels. These stacks can contain a thick top metallization track for high current or RF application. Looking on the metallization systems of liners and cap materials as well as the current carrying metal themselves the differences in the coefficient of thermal expansion (CTE) of the materials lead to intrinsic tension and can result in fatal delamination of the metallization.

The technology evolution worsens the stress level of microelectronic applications. The shrinking, higher interconnect stacks, the diversity of functions, higher frequencies and power densities lead to higher stress and more interaction of effects. At package and assembly level the densification of internal interconnections, the combination of RF, digital, analog and power, new materials like lead free solder, more aggressive processes and 3D packages deliver new challenges for reliability performance. Requirements of harsh environment applications, the use of consumer products in cars or challenging mission profiles for automotive applications trigger new considerations about reliability determination and description, higher robustness and resilience. Presently the processes, design rules, reliability tests and specifications fit to standards which base on established degradation models and quality assurance processes. But the existing standards like electromigration and stress migration tests for interconnects do not cover all of the new requirements especially due to mechanical stress and stress related limits.

Negative Bias Temperature Instability (NBTI) had become one of the most significant device reliability subject reported in this day and age. Not only does NBTI impose a big impact on circuit functionalities as well as product lifetimes, but also becoming the prominent limiting factor for further CMOS technology scaling. Hence accurate characterization and thorough understanding of NBTI is essential to follow or go beyond the Moore’s Law. Nonetheless the existence of NBTI recovery becomes a huge obstruction to this effort; whereby fast reduction in the degradation of the device parameter occurs after end of electrical stress. Moreover device characterization within the measurement stage further increases the NBTI recovery corresponding to the increase in delay.