Partial SOI as a HV platform technology for Power Integrated Circuits

Partial SOI (PSOI) is revisited as a suitable High Voltage (HV) architecture for Power Integrated Circuits (PICs). The added process complexity compared to SOI RESURF is offset by the better heat conduction due to thinner BOX, the wider voltage range capability and the reduced parasitic capacitance to the Handle Wafer (HW). The new proposed platform technology is therefore particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low Ron, fast switching and reduced self-heating are essential. This work reports on the extension of a 200V PSOI process to 400V while providing competitive Ron and low HCI degradation. 

The utilization of Silicon-on-Insulator (SOI) in PIC’s, is very beneficial in many aspects such as low cross-talk, latch-up suppression, and very low leakage currents. Partial SOI substrates are a viable high voltage alternative to thick buried oxide (BOX) SOI substrates, thermally inferior and difficult to manufacture due to high mechanical stress leading to wafer deformation. In PSOI the BOX is patterned and filled with a conductive material to connect the Handle Wafer to the Top Silicon. When used as a high voltage (HV) device architecture, PSOI utilizes a reverse-biased junction depleting the Handle Wafer under the device to support the High Voltage vertically.