A parallel CPU system for deterministic real-time HDL applications. Digital circuit tasks can be transferred to software-executable structures (µEngines) optimized for that workload. Multiple diverse µEngines can operate in parallel, communicating seamlessly while sharing resources to maximize scalability.
 

A 10-bit capacitive SAR-ADC with a sampling rate of 125 kS/s. The ADC converts single-ended input voltages and requires no external S/H circuit. The analog supply voltage is 3.3 V, the digital supply voltage is 1.8 V. The ADC uses the TMIMH module.

A 1.21V band-gap voltage reference with two 2μA current sources, from one supply voltage on VDDA5 (5V typical).

3.3 V CAN transceiver supporting data rates up to 1 Mbps and a standby mode with wake-up via wake-up pattern and is compatible with ISO 11898-2 compliant CAN transceivers.

A high-swing, low-noise clock buffer which ensures clean signal propagation across systems with total load capacitance up to 25pF. It’s optimized to maintain rise/fall times between 1.4ns and 3.1ns to minimize electromagnetic interference (EMI).

Rail-to-rail CMOS free-running high-speed comparator offering 13 ns propgatation delay at 25 mV differential input voltage. A hysteresis can be addded via feedback circuit.

High-speed latched clocked CMOS comparator, built on native NMOS differential pair to reduce offset and offers 19 ns propagation delay at 1 mV differential input signal.