The effect of Fluorine implantation after gate poly deposition and ex-situ Nitrogen anneal after thin gate oxide formation on Time-Dependent Dielectric Breakdown (TDDB) and Negative-Bias Temperature Instability (NBTI) improvement were studied in 0.13um Dual Gate Oxide CMOS Technology for 5V CMOSFETs. The TDDB lifetime was increased by about 1 order for 5V n/p-MOSFET by Fluorine implantation. The 5V p-MOSFET NBTI lifetime is increased an order of magnitude by Fluorine implantation and the ex-situ Nitrogen anneal. A reduction in the Flicker noise and interface trap density was observed for the group with Fluorine implantation and Ex-situ Nitrogen anneal followed by Fluorine implantation. This result demonstrates that optimization of Fluorine and Nitrogen within the gate oxide is necessary for reliability improvement of 5V CMOSFETs in 0.13um technology.

Shallow Trench Isolation (STI) is a very critical Chemical Mechanical Polishing (CMP) process that requires an exceptional planarization state and reduction of micro-scratches is highly vital [1-2]. Minimizing defects has been a challenging task in STI CMP in both traditionally fumed silica slurry and advanced colloidal silica slurry process [3-4]. Furthermore, the use of ceria (CeO2) slurry in STI CMP heightens this difficulty as ceria slurry tends to agglomerate exceedingly easily in contrast to fumed silica slurry. Additionally, vulnerability to micro-scratches in polished wafers increase exceptionally when ceria (CeO2) slurry is utilized in STI CMP.

The design concept of a state of the art 40V to 100V n-channel LDMOS is described in this paper. With aggressively thinner buried oxide (BOX) layer, for the first time, a SOI based power LDMOS has achieved comparable energy capability as Bulk BCD technology.

Tomorrows integrated power electronic systems require more efficient power conversion solutions at lower costs.

Thermal cooling of solder bumps using Under Bump Metalization (UBM) with isotropic undercuts can result in an increase in stress concentration. The stress concentration on the passivation layers can result in cracking, especially when there are surface defects. Opportunities in reducing thermal stress depend on the type of passivation layer design as well as other factors. In Part I of this series of papers, the focus is on optimizing the thickness of the standard passivation design.

Surface undulations on semiconductor devices can increase chip package interaction stress that leads to possible passivation cracking. This is especially so for flip chip interconnects which have solder balls that are in contact with the passivation layer. The solder balls have a larger Coefficient of Thermal Expansion (CTE) compared to the passivation layers and this can lead to increase in fracture rate especially during reflow cooling. The other factor is the underfill material.

Integration of Back End Of Line (BEOL) CMOS technologies with Wafer Level Packaging (WLP) is challenging, as mismatch of Coefficient of Thermal Expansion (CTE) between materials can result in thermo-mechanical induced cracking. This is especially true during reflow cooling of wafers after the solder ball attach process. Factors that contribute towards cracking can be from both the BEOL as well the WLP process steps.