An original work in developing technology that allows the integration of multiple vertical power devices within Power ICs has been presented in this manuscript. The developed technology uses a combination of top and back trenches as well as wafer sawing to achieve complete dielectric isolation between the silicon islands. Each silicon island is capable of holding either single vertical power device or CMOS circuitry. The test structures have been manufactured, wafer diced and individual chips packaged and tested initially for mechanical and thermal stability.

The feasibility of EEPROM memories in SOI process technologies has been proven. It has also been shown that known data retention problems at high temperatures caused by leakage currents can be solved without extra circuitry. In this paper results of EEPROM cell matrix measurements regarding functionality and reliability will be presented. Different cell designs will be compared. Furthermore, a 32x16 bit EEPROM prototype and memory test results will be shown.

During the evolution of RF bipolar transistors, much efforts were spent to optimize the base design. Device engineers came up with concepts like graded dopant profiles, SiGe and SiGe:C base layers, elevated base structures, etc. Regarding the collector, selectively implanted collectors (SIC) were introduced to increase both the cutoff frequency ft and the maximum frequency of oscillation fmax. In this work we focus on the collector-emitter breakdown voltage BVCE0 and its relation to ft for differently designed SICs of Si-based RF bipolar transistors.