Find our technical papers, webinars, articles
The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.
49 entries found
Rapid Thermal Processing (RTP) → key process in microelectronics
Use of large temperature range & varying processing times; Control of tool stability for high quality results; Tool Monitoring.
Temperature dependent monitoring by change of sheet resistance (Rs); Different wafer preparation for different temperature ranges; Repeatability and long-term stability investigations
Abstract — In semiconductor manufacturing, surface defects on wafers must be classified accurately for better yield management. To manage the increasing chip demand in speed and scale, automatic defect classification (ADC) system has been introduced. Most existing ADC systems utilize machine learning-based algorithms that require manual feature extractions and manual intervention such as human-based classification for accuracy and consistency. These methods are labour-intensive, unreliable, and highly prone to human error. Therefore, by leveraging on deep learning technologies, this paper proposes DLADC - an ADC system using a deep convolutional neural network (CNN) architecture for detecting and classifying semiconductor wafer surface defects. The proposed system takes Scanning Electron Microscope (SEM) images as input and outputs the defect’s class and location. The proposed system also sub-classifies particle-type defects into various sizing groups. Identification of defect types that occurred on wafer surfaces allows for better defect root cause analysis, and the additional information of defect size further serves as an essential indication of the origin of machine failure. The proposed DLADC promotes 2x time saving while achieving an improved accuracy of 93.69% based on experimental results with a real semiconductor defect dataset. Not only does DLADC outperforms the 70% classification performance of trained operators, but it also surpasses the 90% classification performance of industrially pragmatic defect classification.
- Micro-Transfer-Printing (µTP) was introduced as a new and promising technology for 3D- and heterogeneous integration.
- The main advantage of µTP is the parallel placement of up to thousands of small chiplets with a very high printing accuracy.
Effects of 3D Profiles of Adjacent Trench Areas on Rule-Based Etch Bias Retargeting Accuracy for OPC
The shrinkage of critical lithographic feature size keeps introducing new challenges to the standard rule-based etch bias retargeting of Optical Proximity Corrections (OPC). This motivates the use of model-based instead of conventional rule-based etch bias retargeting. On the other hand, model-based retargeting comes with a substantial increase in run-time and complexity.
Wire bonding is an important process of semiconductor assembly by providing electrical connection between integrated circuit and the external leads of semiconductor package. Wire bonding on none-flat surface is uncommon and less exploration as compare to flat surface bond pad. In certain circumstances, wire bonding is required to conduct on none-flat surface. Bond pad with concave surface is initially designed for solder bumping.
Do you know what happens to your IC design once you have taped-out to your foundry?
This webinar will shed some light on the various techniques applied in the process from design submission to mask generation. You will learn about the Data Input Check performed by X-FAB to ensure the best possible fabrication quality and how scribe lane structures are added allowing the monitoring of key process parameters. It will also address how the mask generation flow is optimized for different prototyping scenarios such as Single Layer Masks (SLM) and Multi Layer Masks (MLM). In addition, practical suggestions will be provided on how to bypass the reticle limitations by using stitching for large layouts.
In this webinar, we will showcase the different prototyping services X-FAB offers so that you can make the most of your designs and get it first-time-right.
One of the key trends in medical science is the personalization of health care: the analysis of the patient’s characteristics and physical condition, and the individual adaptation of medical treatment. An important cornerstone for this trend is the introduction of Lab-on-Chip technology which enables the analysis of minute quantities of biological sample material or liquid - resulting in the generic term “Microfluidics”.
Microchips in microfluidic applications use common functional elements based on MEMS processes, e.g. fluidic channels and chambers, electrodes or injection ports. Due to the variety of applications and the various players entering this market there is – to date – no standardized approach to realize these functional elements. X-FAB started an effort to address this challenge by setting up the X-FAB Microfluidic Platform, with the goal to support customers with cost-effective, silicon-proven solutions enabling faster time to market. This webinar will provide an overview of typical building blocks of a Lab-on-Chip device and technical solutions based on the capabilities available through X-FAB’s MEMS foundry services
Shallow Trench Isolation (STI) is a very critical Chemical Mechanical Polishing (CMP) process that requires an exceptional planarization state and reduction of micro-scratches is highly vital [1-2]. Minimizing defects has been a challenging task in STI CMP in both traditionally fumed silica slurry and advanced colloidal silica slurry process [3-4]. Furthermore, the use of ceria (CeO2) slurry in STI CMP heightens this difficulty as ceria slurry tends to agglomerate exceedingly easily in contrast to fumed silica slurry. Additionally, vulnerability to micro-scratches in polished wafers increase exceptionally when ceria (CeO2) slurry is utilized in STI CMP.
Micro-Electro-Mechanical-Systems (MEMS) are bridging as sensors and actuators the gap between the real analogue word and the digital world with their enormous data processing and data storage possibilities. MEMS solutions are providing significant advantages: small form factors allow the integration of sensors in miniaturized systems and their manufacturing in modern wafer processes makes them available in very high amounts at quite low costs.
The shift of the threshold voltage (Uth) in high voltage metal-oxide-semiconductor field effect transistors (n-MOSFET) with source and drain regions created by an As-implantation with different implanters was investigated. By analyzing the capacitance-voltage curves recorded in metal-oxide-semiconductor structures with different thicknesses of SiO2 and different shapes we found that the shift of Uth in the n-MOSFETs was correlated with the presence of implantation induced defects in the gate oxide. These defects were stable even after the heat treatments at about 1200 K and they appeared in SiO2 due to different pressures in the implantation chamber and different types of gas.