ResourceXplorer: X-FAB

Find our technical papers, webinars, articles

The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.

324 entries found

Surface Protection for Semiconductor Direct Bonding

Published: Oct 2016

Semiconductor direct wafer bonding is a widely used process for fabricating 3-dimensional structures, especially engineered substrates such as SOI wafers or cavity wafers with and without insulating layers at the bonding interface. The investigations described here concern cavity SOI wafers without insulating layers, as used for discrete and integrated pressure sensors.

Posted in: Paper --- Technical Categories: MEMS, More than Moore, Wafer Manufacturing

3D structure SOI cavities wafer bonding pressure sensors absolute pressure sensors piezo-resistive piezoresistive pressure sensors BOE etching oxide stripping

Effect of Silicon Nitride Deposition Parameters on TDDB performance of SiNx-MIM Capacitors

Published: Sep 2016

Silicon nitride (SiNx) is commonly used as the dielectric or insulator material for metal-insulator-metal (MIM) capacitors. The deposition of SiNx can be performed using plasma-enhanced chemical vapor deposition (PECVD) method with different deposition parameters by changing individually the SiH4 flow rates, NH3 flow rates, RF power, substrate temperature, etc. Time-dependent dielectric breakdown (TDDB) is the most important reliability test item to check the intrinsic performance of the MIM capacitor dielectrics.

Posted in: Paper --- Technical Categories: Analog, Reliability

MIM capacitors capacitors metal-insulator-metal capacitor time-dependent dielectric breakdown TDDB lifetime performance optimization Fluid flow Radio frequency Silicon nitride Metals SiNx dielectric material insulator material lasma-enhanced chemical vapor deposition method PECVD method reliability testing gas flow rate

Reliability Evaluation of Tungsten Donut-Via as an Element of the Highly Robust Metallization

Published: Sep 2016

The typical via layout in AlCu-metallizations with tungsten via is cylindrical. Common vias have a size as small as possible. More challenging application, temperature and mission profiles require higher robustness of a metallization. Via arrays of small common vias are in use to transfer higher currents. But the typical via array layout is not the best layout for applications which are faced to high mechanical stress.

Posted in: Paper --- Technical Categories: Reliability, Simulation

interconnect reliability design robustness high temperature AlCu Al/Cu metallization robust current density ANSYS electromigration electro-migration high current Donut-Via via array COSMOL thermal stress simulation

Detection and Analysis of Stress-induced Voiding in Al-Power lines by Acoustic GHz-Microscopy

Published: Sep 2016

The formation of voids in metal layers upon stress-induced migration is a well-known defect mechanism in integrated circuits. This phenomenon largely accelerates with increasing ambient temperature. Consequently, the occurrence and the growth of voids result in an increased electrical resistivity which once more leads to an acceleration of the growth rate highly impacting the reliability and the life span of the device. Technological improvements aim at the minimization of stress induced voiding. However, for understanding and optimization of process related factors nondestructive methods for screening and systematic monitoring of the void formation e.g. during stepwise reliability testing are required.

Technical Categories: Reliability

metallization metal line stress SEM TiN thermo mechanical thermo-mechanical electromigration electro-migration migration effects GHz-SAM acoustic GHz-microsopy AlCu MATLAB stress voiding PVD hydrogen

Making the Handling of Complex & Diverse IC Designs Easier by Using X-FAB’s SpecXplorer Tool

Published: Sep 2016

Designs are becoming more complex with different parts of the design often being developed by separate teams across the globe. Whilst X-FAB’s open platform processes offer a huge flexibility and modularity, they are also complex in terms of required and forbidden module combinations. This webinar will show how we can help you set up your development projects in the right way to work efficiently together in a large, distributed team, to avoid any conflict when combining the different parts of the design, and to meet your timelines and cost targets.

With the SpecXplorer, X-FAB offers a comprehensive, easy-to-use web application with powerful filter and search capabilities. Instead of going through hundreds of pages of PDF documents, this tool supports a fast and easy comparison between different process families, helps you find the right module combination for selected devices and enables you to filter the process data to what you really need for your project. A recent addition of SpecXplorer now supports a consistent usage of the module and device selection throughout the design flow by interfacing with X-FAB’s comprehensive project setup scripts.

Posted in: Webinar Recording --- Technical Categories: SpecXplorer

0.35 μm technology 0.35µm

CMOS integrated UV-Photodiodes

Published: Sep 2016

Highly sensitive UV-Photodiodes integrated in a versatile high voltage capable analogue 0.18 μm CMOS technology have been developed.

Posted in: Paper --- Technical Categories: CMOS, Characterization, More than Moore, Opto

CMOS sensors spectral sensitivity dark current XH018 UV Photodiode Cross Talk Suppression Dark Reference

Alternative level shifting devices for 900V gate drivers

Published: Aug 2016

With increasing operating voltages the size of high voltage transistors used as level shifters increases tremendously. For 900V applications the area consumption would get cost critical. Alternative level shifting concepts make use of capacitive, inductive or optical coupling. The appropriate integrated high voltage devices were developed and investigated.

Posted in: Paper --- Technical Categories: More than Moore, High-Voltage, SOI, Characterization, Simulation

integrated high voltage devices level shifter trench isolated SOI UVLO under voltage lock out circuit IGBT 900V quasi vertical DMOS capacitive coupling inductive coupling optical metal organic vapour phase epitaxy MOVPE LED

A study on device robustness with integrated effects from low parts-per-billion level of metallic elements in wafer cleaning process chemicals

Published: Jul 2016

The existence of metallic elements in incoming chemicals is one of the great concerns in fab processing, degrading the fabricated device properties. In particular, with the unknown handling activity and environment influence caused by different means of transportation on the incoming chemicals stored typically in drum packaging, tight specifications in terms of various metallic species need to be enforced. These metallic impurities, if not controlled, are then introduced to the device during wafer fabrication especially during wafer cleaning process steps, with the contaminated incoming chemicals. Even trace amounts in metal concentration may alter the device electrical properties at their operating condition or even cause significant degradation over time. The impacts are especially critical on dielectric (gate oxide) quality. Correlation of such impact on device with respect to the metallic concentration level can help in setting references for reasonable specification limits, while not jeopardizing the device characteristics as well as its reliability.

Posted in: Paper --- Technical Categories: Wafer Manufacturing, Reliability

Logic gates threshold voltage cleaning reliability wafer processing wafer fabrication Contamination Chemical elements wafer level packaging metallic concentration level device robustness integrated effects metallic elements wafer cleaning process chemicals drum packaging

First-Time-Right Webinar Series (Part IX): ESD Verification Made Easy - How the ESD Design Checker Tool Enables HBM Robustness Simulation

Published: Jul 2016

Nowadays, achieving Human Body Model (HBM) robustness levels from 2kV up to 8kV is a requirement for nearly every newly-designed IC. Designing ESD-robust analog/mixed-signal devices can be a challenging and often daunting task for designers. ESD simulation of integrated circuits from device level up to full chip level is therefore needed to reach this goal without multiple design iterations.

This webinar will showcase how these challenges can be addressed using X-FAB’s ESD Design Checker tool which enables a “virtual“ ESD test on circuit level at an early design stage, providing a first rough estimation of the ESD robustness of the IC. The tool helps in determining ESD discharge paths and identifying possible ESD weak points, thus enabling designers to reduce design cycle time and to achieve first-time-right functional silicon.

Posted in: Webinar Recording --- Technical Categories: First-Time-Right, ESD, Modeling

ESD cells ESD HV I/O library ESD ESD robustness ESD solutions robustness Human Body Model HBM transmission line pulsing transmission line pulse snap-back Cadence XH018

Implant ions charging influence in gate dielectrics within isolated closed TUB SOI wafers

Published: Jul 2016

In this work, we studied the gate dielectric integrity within the isolated closed TUB constructed by deep trench isolation in SOI process wafers. Slight reduction in the range of few Volts was detected occasionally from TZDB test assessment on thick gate oxide; verifying among different possible failure mechanisms base on evaluation study, it is found to be most sensitive induced by charging effects to the Gate dielectric layers during various HE, MC implantation process steps.

Technical Categories: Process development, Reliability, Characterization

dielectric integrity silicon-on-insulator implant induced charges trapped extrinsic defect density TZDB time zero dielectric breakdown PFG plasma flood gun closed TUB with DTI deep trench isolation high energy HE medium current MC implantation defect density D0