ResourceXplorer

Find our technical papers, webinars, articles

The ResourceXplorer enables you to access technical papers, webinars and articles related to analog/mixed-signal semiconductor technologies.



308 entries found



Use of MIMO and beamforming to increase the radiated power. Challenges:

  • Performances: at mmWave frequencies, it is important to minimize loss and locate the front-end components close to the radiating elements.
  • Mechanicals: the spacing between phased-array elements (λ/2) becomes too small, 5.3 mm at 28 GHz.

Be aware of the avalanche! Learn how an avalanche photodiode (APD) works and see which devices X-FAB is offering for integration in its modular high voltage XH018 process.
Everybody is talking about single photon avalanche diodes (SPAD) for LiDAR and Time-of-Flight. Do you know what is required to upgrade from an APD to a SPAD? How can a good active quenching circuit be designed?
The webinar will introduce newly-developed APD and SPAD devices. You will be provided with information about the key parameters and learn how to integrate them into X-FAB’s process. X-FAB is offering a reference circuit for active quenching: discover how it works and how it could reduce your time for design.

Have you ever sat in front of your IC layout and asked yourself how you need to place guard rings to mitigate unwanted parasitic effects?
If you take the safe approach you may waste precious layout area which increases the overall footprint of your IC. Just imagine if you could know where peaks of substrate current are in order to effectively predict the parasitic effects for countermeasures. To address this challenge X-FAB has enabled PNAware XSUB – a substrate analysis tool developed by the Swiss EDA software vendor PN Solutions.

In this webinar, we will demonstrate the tool which is enabled by X-FAB's PDK environment using examples from the 180 nm high-voltage technology (XH018).

Adhesive wafer bonding using laminated photosensitive dry-resist offers many advantages and can be used to realize advanced, CMOS integrated, volume manufacturable lab-on-a-chip devices. The relatively low bond temperatures involved allow the wafer-level hybrid integration of a range of substrates, e.g. CMOS wafers with structured MEMS glass wafers. The dry-film polymer acts as the adhesive interlayer and can also be lithographically patterned to form sealed microfluidic fluid channels and chambers after the bonding process.

Published: Jul 2019

System in package (SiP): a number of ICs or chips are mounted in a single carrier package. Dies may be arranged horizontally or stacked vertically on a substrate, internally connected by: fine wires that are bonded to the package; flip chip technology, solder bumps are used to join stacked chips together; Vertical connections by Through Silicon Vias (TSV)

The shrinkage of critical lithographic feature size keeps introducing new challenges to the standard rule-based etch bias retargeting of Optical Proximity Corrections (OPC). This motivates the use of model-based instead of conventional rule-based etch bias retargeting. On the other hand, model-based retargeting comes with a substantial increase in run-time and complexity. 

Wire bonding is an important process of semiconductor assembly by providing electrical connection between integrated circuit and the external leads of semiconductor package. Wire bonding on none-flat surface is uncommon and less exploration as compare to flat surface bond pad. In certain circumstances, wire bonding is required to conduct on none-flat surface. Bond pad with concave surface is initially designed for solder bumping. 

Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.

The reliability of CMOS circuits is influenced by local inhomogeneities in current density, temperature and mechanical stress. Mechanical stress caused by processing and post-processing sources like material mismatch, temperature steps and extrinsic sources like bonding, 3D integration and extended operating conditions becomes more and more relevant the for reliability. It can affect the life time performance of interconnects as well as the function of active devices like stress sensitive transistors.

A Re-design root cause in Smart Power ICs, like motor drivers. Some customers are affected by Re-designs due to unwanted substrate coupling, Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem. Not locally concentrated. AC simplifications do not work.