284 entries
Published: Jun 2011

Photo detector integrated circuits (PDIC) require high-sensitivity and high-bandwidth photo diodes for the latest generation of Blu-ray data storage devices. Due to the very short 405nm wavelength used, carriers are generated close to the surface. Standard photo diodes have only a low sensitivity for blue light. Therefore, special adapted photo diodes are necessary to support sensitivity higher than 0.25A/W for a 405nm wavelength.


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Published: Jun 2011

In this paper, micromachined acceleration sensors as ready-to-use Intellectual-Property-Blocks (IP-Blocks) are introduced. These standard elements are available for a special surface micromachining foundry technology. They are ready to use, characterized and qualified design elements, which can be customized by changing the peripheral elements such as bond pads, and allow the fast prototyping and production start of high-performance inertial sensors.


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Published: May 2011

In this paper we present a modular trench isolated high voltage SOI process with the possibility to integrate various types of high voltage transistors. The integration of these additional 650 V devices takes place in a modular approach which allows a high process flexibility to support different applications with a minimum number of additional or changed process steps.


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Published: Mar 2019

First simulations which support the development work for optimized interconnect layouts as features to improve the reliability of a circuit were prepared. The evaluations started with the heater development of self-heating test structures for higher metal layers for accelerated reliability tests. It continued with the development of a high robust metal stack. The simulations and the tests at heaters and high robust metallization test structures demonstrated the advantages of such a layout improvement.


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Published: May 2011

Successful integration of 100V LDMOS devices in 0.35μm CMOS technology is presented in this paper. These integrated devices are enhanced N-type and P-type LDMOS which are compatible with thin (14nm) and thick (40nm) layers of gate oxide. A breakdown voltage of more than 100V with RDS (ON) =200/180mΩ.mm2 for N-type LDMOS and RDS (ON) =690/640mΩ.mm2 for P-type LDMOS with 14nm/40nm gate oxide thickness.


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Published: Mar 2019

Harsh wafer level probing has a higher chance of causing inter metal dielectric (IMD) cracking compared to wire bonding. This work explores the stress induced by probing by utilizing dynamic Finite Element Analysis (FEA) structural mechanics simulation. A thicker bond pad (METTHK with thickness of 3000 nm) can reduce the IMD stress caused by harsh wafer level probing.


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Published: May 2011

This paper demonstrates and explains the effects of hot carrier injection and interface charge trapping correlated with impact ionization under normal on-state conditions in a highly dense low-resistance Super-Junction LDMOSFET. The study is done through extensive experimental measurements and numerical simulations using advanced trap models.


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Published: Apr 2011

Silicon photodiode integrated with CMOS has been in extensive study for the past ten years due to its wide use in applications such as short-distance communication, VCD players, ambient light sensors and many other intelligent systems. In recent years, high speed blue-ray DVD is replacing conventional DVD due to its larger storage capacity and higher speed. In this work, the photodiode optimized for blue ray is fully integrated with standard 0.35um CMOS process and the bandwidth dependency upon thermal process and epitaxial material is investigated.


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Published: Jul 2019

Adhesive wafer bonding using laminated photosensitive dry-resist offers many advantages and can be used to realize advanced, CMOS integrated, volume manufacturable lab-on-a-chip devices. The relatively low bond temperatures involved allow the wafer-level hybrid integration of a range of substrates, e.g. CMOS wafers with structured MEMS glass wafers. The dry-film polymer acts as the adhesive interlayer and can also be lithographically patterned to form sealed microfluidic fluid channels and chambers after the bonding process.


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Published: Mar 2011

Drastically device dimension shrinkage and rigorous requirement in automotive era puts Negative Bias Temperature Instability (NBTI) at the forefront of reliability issue recently. The PMOS parametric degradation during negative bias high temperature aging can depend on many process variables of the manufacturing flow. A study was carried out to explore the process related dependencies for high voltage PMOS transistor and to increase the device robustness against NBTI stress. In this papers, the process impact on the NBTI degradation were discussed. This investigation work provides methods for significant suppression of the NBTI degradation with silicon rich oxide (SRO) inter layer dielectric (ILD) liner and two-step gate oxidation.


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