284 entries
Published: Sep 2016

Designs are becoming more complex with different parts of the design often being developed by separate teams across the globe. Whilst X-FAB’s open platform processes offer a huge flexibility and modularity, they are also complex in terms of required and forbidden module combinations. This webinar will show how we can help you set up your development projects in the right way to work efficiently together in a large, distributed team, to avoid any conflict when combining the different parts of the design, and to meet your timelines and cost targets. With the SpecXplorer, X-FAB offers a comprehensive, easy-to-use web application with powerful filter and search capabilities. Instead of going through hundreds of pages of PDF documents, this tool supports a fast and easy comparison between different process families, helps you find the right module combination for selected devices and enables you to filter the process data to what you really need for your project. A recent addition of SpecXplorer now supports a consistent usage of the module and device selection throughout the design flow by interfacing with X-FAB’s comprehensive project setup scripts.


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Published: Sep 2016

They provide high effective quantum efficiency (EQE 30 – 80 %) across the visible spectrum down to the vacuum UV and come on the cost of only a small modification to the core CMOS process. A single and a double junction diode as well as their dark reference devices and a special UV reference device for each are presented.


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Published: Aug 2016

With increasing operating voltages the size of high voltage transistors used as level shifters increases tremendously. For 900V applications the area consumption would get cost critical. Alternative level shifting concepts make use of capacitive, inductive or optical coupling. The appropriate integrated high voltage devices were developed and investigated.


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Published: Jul 2016

The existence of metallic elements in incoming chemicals is one of the great concerns in fab processing, degrading the fabricated device properties. In particular, with the unknown handling activity and environment influence caused by different means of transportation on the incoming chemicals stored typically in drum packaging, tight specifications in terms of various metallic species need to be enforced. These metallic impurities, if not controlled, are then introduced to the device during wafer fabrication especially during wafer cleaning process steps, with the contaminated incoming chemicals. Even trace amounts in metal concentration may alter the device electrical properties at their operating condition or even cause significant degradation over time. The impacts are especially critical on dielectric (gate oxide) quality. Correlation of such impact on device with respect to the metallic concentration level can help in setting references for reasonable specification limits, while not jeopardizing the device characteristics as well as its reliability.


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Published: Jul 2016

Nowadays, achieving Human Body Model (HBM) robustness levels from 2kV up to 8kV is a requirement for nearly every newly-designed IC. Designing ESD-robust analog/mixed-signal devices can be a challenging and often daunting task for designers. ESD simulation of integrated circuits from device level up to full chip level is therefore needed to reach this goal without multiple design iterations.

This webinar will showcase how these challenges can be addressed using X-FAB’s ESD Design Checker tool which enables a “virtual“ ESD test on circuit level at an early design stage, providing a first rough estimation of the ESD robustness of the IC. The tool helps in determining ESD discharge paths and identifying possible ESD weak points, thus enabling designers to reduce design cycle time and to achieve first-time-right functional silicon.


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Published: Jul 2016

In this work, we studied the gate dielectric integrity within the isolated closed TUB constructed by deep trench isolation in SOI process wafers. Slight reduction in the range of few Volts was detected occasionally from TZDB test assessment on thick gate oxide; verifying among different possible failure mechanisms base on evaluation study, it is found to be most sensitive induced by charging effects to the Gate dielectric layers during various HE, MC implantation process steps.


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Published: Jun 2016

Today’s state-of-the-art SOI processes support very compact deep-trench-isolated high-voltage devices with a significantly smaller footprint than is possible with conventional isolation schemes, fulfilling the needs of the growing smart power IC market. While the low RDSon of these devices helps to create very area-efficient drivers, it introduces new challenges to the design of the metal interconnect and the distribution of high current densities.
This webinar will discuss how these challenges can be addressed using the latest design and verification tools. In addition, possibilities for layout automation using a pcell-based driver metallization will be shown. This highly automated layout flow enables designers to quickly evaluate several different layout variants and architectures avoiding error-prone manual layout.


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Published: May 2016

Ideas is to perform a “virtual“ ESD test on circuit level in an early design stage; first rough estimation about HBM ESD robustness; determine ESD discharge paths; find possible ESD weak points; reduce the design cycle time; enable First Time Right.


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