285 entries
Published: Mar 2019

First simulations which support the development work for optimized interconnect layouts as features to improve the reliability of a circuit were prepared. The evaluations started with the heater development of self-heating test structures for higher metal layers for accelerated reliability tests. It continued with the development of a high robust metal stack. The simulations and the tests at heaters and high robust metallization test structures demonstrated the advantages of such a layout improvement.


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Published: Mar 2019

A Re-design root cause in Smart Power ICs, like motor drivers. Some customers are affected by Re-designs due to unwanted substrate coupling, Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem. Not locally concentrated. AC simplifications do not work.


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Published: Mar 2019

A frequent Re-design root cause in Smart Power ICs, like motor drivers: parasitic Substrate Couplings. Today these problems are handled by hand, Trial & Error by very experienced designers after measured silicon: time consuming. Substrate coupling is an active and distributed large signal problem, not locally concentrated, AC simplifications do not work.


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Published: Jan 2019

Do you know what happens to your IC design once you have taped-out to your foundry?
This webinar will shed some light on the various techniques applied in the process from design submission to mask generation. You will learn about the Data Input Check performed by X-FAB to ensure the best possible fabrication quality and how scribe lane structures are added allowing the monitoring of key process parameters.  It will also address how the mask generation flow is optimized for different prototyping scenarios such as Single Layer Masks (SLM) and Multi Layer Masks (MLM). In addition, practical suggestions will be provided on how to bypass the reticle limitations by using stitching for large layouts.

In this webinar, we will showcase the different prototyping services X-FAB offers so that you can make the most of your designs and get it first-time-right.


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Published: Dec 2018

One of the key trends in medical science is the personalization of health care: the analysis of the patient’s characteristics and physical condition, and the individual adaptation of medical treatment. An important cornerstone for this trend is the introduction of Lab-on-Chip technology which enables the analysis of minute quantities of biological sample material or liquid - resulting in the generic term “Microfluidics”. 

Microchips in microfluidic applications use common functional elements based on MEMS processes, e.g. fluidic channels and chambers, electrodes or injection ports. Due to the variety of applications and the various players entering this market there is – to date – no standardized approach to realize these functional elements. X-FAB started an effort to address this challenge by setting up the X-FAB Microfluidic Platform, with the goal to support customers with cost-effective, silicon-proven solutions enabling faster time to market. This webinar will provide an overview of typical building blocks of a Lab-on-Chip device and technical solutions based on the capabilities available through X-FAB’s MEMS foundry services


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Published: Nov 2018

  • ELDO Monte Carlo
  • Background of OCC/ SOA
  • OCC Viewer (XOCV)
  • Density Checks and Dummy Generation
  • Voltage Dependent Checks
  • Floating Gate Check


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Published: Oct 2018

Shallow Trench Isolation (STI) is a very critical Chemical Mechanical Polishing (CMP) process that requires an exceptional planarization state and reduction of micro-scratches is highly vital [1-2]. Minimizing defects has been a challenging task in STI CMP in both traditionally fumed silica slurry and advanced colloidal silica slurry process [3-4]. Furthermore, the use of ceria (CeO2) slurry in STI CMP heightens this difficulty as ceria slurry tends to agglomerate exceedingly easily in contrast to fumed silica slurry. Additionally, vulnerability to micro-scratches in polished wafers increase exceptionally when ceria (CeO2) slurry is utilized in STI CMP.


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Published: Oct 2018

Even though image sensors have become smaller and smaller in the past years for usage in mobile phone and digital cameras, there are still applications which require large image sensors. For example, X-Ray sensors are used in a wide range of medical, industrial and scientific applications. Such large pixel designs come with their specific design challenges especially if they have to been read out fast.
In this webinar X-FAB will showcase its 0.18 µm CMOS process (XS018) that is particularly well-suited for image sensors. The presentation will focus on large pixel designs. Several pixel layouts with different photodiode shapes have been tested and characterized. You will learn about the pros and cons with regards to speed, full well capacity and image lag for the these layout structures. Register now to find out how your pixel design can be optimized!


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Published: Oct 2018

The optimization of a metal-Schottky source-drain NMOS structure and it’s underlying parasitic lateral BJT has been performed on a 0.18 um feature size BCD power IC process. The metal-Schottky structure is fabricated using an ultra-shallow ion implantation which is capable of modifying the barrier height without the need for introduction of non-standard metal systems into the CMOS fab.


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Published: Sep 2018

CMOS-MEMS integration is getting a more and more important topic with growing expectations and requirements on the function and performance of micro sensors [1]. The integration of ASICs and memories to MEMS sensor structures allows by calibration the compensation of side effects (temperature influences, stress influences,…) and manufacturing tolerances.


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