8b-20 Msps ADC with 4 :1 Mux
ADC
EASii IC
0.18 μm
XP018
VS
Layout
Schematic
High Speed 8 bits ADC running at 20 MSps including an analog multiplexer 4:1 Only 2 clock latency power :22mW Voltage supply: 3.3V
TI-RF-CMP
Comparators
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic
TI-RF-CMP is a low power CMOS RF comparator with 4 ns propagation delay and latch function. ESD protection provided.
TI-RF-DRV
Driver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic
TI-RF-DRV is a fully differential RF driver for differential signal processing applications. Common-mode level of differential outputs is adjustable that allows to shift easily the input signals for driving single-supply ADCs. ESD protection provided.
TI-RF-MUX
Multiplexer
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic
TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 devices as one 8-to-1 multiplexer. ESD protection provided.
TI-RF-Switch
Analogue Switches
Thesys-Intechna
0.35 μm
XH035
VS
GDSII
Schematic
The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches. Used CMOS technology provides high isolation and low insertion loss at frequencies up to 1 GHz.
TI-16PI/150M
ADC
Thesys-Intechna
0.18 μm
XT018
VS
GDSII
Schematic
TI-16PI/150M is a dual-channel fully differential 16-bit ADC with pipelined architecture optimized for high dynamic performance at sample rates up to 180 MSPS.
TI-Manchester
Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic
TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...
S8
Microprocessor
easics NV
All Geometries
All Processes
VS
VHDL
Verilog
S8 processor/microcontroller: This is a tiny, customizable microcontroller core, available in 8-bit data widths for house keeping of mixed-signal ASICs.
TCP Offload Engine
Other
easics NV
All Geometries
All Processes
VS
VHDL
Verilog
Easics' TCP Offload Engine (TOE) can be used to offload the TCP/IP stack from the CPU and handle it in ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible.
TI-DR-H&LS
Driver
Thesys-Intechna
1.00 µm
XDH10
VS
Schematic
The driver is a high-voltage device, manufactured with SOI technology. It has a driver structure that enables ti drive independent referenced channel power MOS or IGBT. The upper (floating) section is enabled to work with voltage rail up to 600 V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.
TI-DR-LS
Driver
Thesys-Intechna
0.60 µm
XT06
VS
Schematic
The dual high-speed gate drivers are especially well suited for driving the MOSFETs and IGBTs. Each of the two outputs can sourse and sink 4A of current while producing voltage rise and fall times of less than 10 ns. Low propagation delay and fast, matched rise and fall times make the driver ideal for high-frequency and high-power applications.
aopac01
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac01 is an internally compensated general purpose OpAmp with P-MOS input and common-source output stage.
aopac02
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac02 is an internally compensated rail-to-rail input/output OpAmp.
aopac03
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac03 is an internally compensated general purpose OpAmp with N-MOS input and bipolar pnp output stage.
aopac04
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac04 is a internally compensated general purpose OpAmp with P-MOS input stage.
aopac05
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac05 is a fast internally compensated OpAmp with P-MOS input stage.
aopac06
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac06 is a high-gain, high load current CMOS OpAmp with N-MOS input and rail-to-trail output stage.
aopac07
Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aopac07 is a general purpose internally compensated OpAmp with P-MOS input and source follower output stage.
acmpc01
Comparators
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. acmpc01 is a general purpose voltage comparator with P-MOS input and hysteresis.
acmpc03
Comparators
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. acmpc03 is a general purpose, low-consumption voltage comparator with N-MOS input.
acmpc04
Comparators
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. acmpc04 is a general purpose, low power voltage comparator with P-MOS input.
abgpc01
Bandgaps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. abgpc01 is a bandgap reference with well resistors.
abgpc02
Bandgaps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. abgpc02 is a bandgap reference with Poly2 resistors. The cell doesn’t include an output buffer.
abgpc03
Bandgaps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. abgpc03 is a bandgap reference with Poly2 resistors. The cell doesn’t include an output buffer.
abiac01
Bias
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. abiac01 is a general purpose VTH - based current reference. The circuit forces a current of 2.4μA (approx.) to flow through P- or N-MOS transistor with a W/L ratio of 10μm/6μm.
abiac02
Bias
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. abiac02 is a general purpose weak inversion bias cell. The circuit forces a current of 250nA (approx.) to flow through P- or N-MOS transistors with a W/L ratio of 10μm/10μm.
achpc01
Charge Pumps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. achpc01 is doubling charge pump 5V to 8.75V.
achpc02
Charge Pumps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. achpc02 is a 4-stage Dickson charge pump originally designed for EEPROM.
arcoc01
Oscillator
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. arcoc01 is a 200kHz fixed frequency, current balancing RC oscillator with internal R and C.
arcoc02
Oscillator
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. arcoc02 is a 200kHz adjustable current balancing RC oscillator with internal R and C.