IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
Securyzr Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure-IC Securyzr provides a complete range of security features while addressing all the state-of-the-art threats against embedded systems. Securyzr is customized according to each market's and client's specific requirements.

TRNG Security
Secure-IC
All Geometries
All Processes
PT
GDSII

True Random Number Generators are used to generate statistically independent sets of bits for various applications such as One Time Pad cryptography, key generation, seeds for PRNGs, masks to protect an implementation against side-channel analysis.

Tunable Cryptography Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Symmetric Cryptography, Asymmetric Cryptography, Hash and MAC functions. Embedding the state-of-the-art countermeasure against high order side-channel attacks, Tunable Crypto IP allows you to reach the perfect balance between Security, Speed, and Area.

HT_MUX_16:1 Multiplexer
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

High Temperature Analog Mux with >50dB isolation and Ron=, Area=0.1mm2, 1dB Compression Current 2mA, Off Isolation Rejection 60dB, Insertion Loss 0.5dB. Verified by Simulation for XH035.  

HT_CSC Current Sensor
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Programmable Trip Current Sense Instrumentation Amp and Comparator.  Differential input assumes 0.01Ω sense resistor. Gain prog of 19x or 38x. FSR=50mV/100mV. Trip Voltage 40/60/90 mV. Latched comparator o/p. Verified by Simulation for XH035.

HT_HRM Other
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Harmonic Reject Mix, Idd=10mA, Area=1mm2, Gain 12dB, 1dB Compression =2Vpp.  Can be simplified (reduce area & power) or simply configured as standard Mixer. Verified by Simulation for XH035.

HT_OSC_8M Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

-40°C-> 220°C Integrated Oscillator Clock Generator, Nominal 8MHz, Vdd=3.3V, Idd=1mA, Variation over supply & temp <5%, 8b DAC for process trim to <1%. Requires low tempco reference current (IP Available). Verified by Simulation for XH035.

HT_PGA Other
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

IF Programmable Gain Amp, Gain Range 6->24dB, Gain Step 6dB, B/W 240kHz, 1dB Compression 5Vpp, Idd=2mA, Area=2mm2. Verified by Simulation for XH035.

HT_LNA_TIA LNA
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Low Noise Transimpedance Amplifier/LNA,Transimpedance 900Ω/3.6kΩ, 1dB Compression 400mVpp, Idd=10mA, Area=1mm2. Verified by Simulation for XH035.

HT_Frac_PLL PLL
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Fractional_N PLL developed for low-noise fractional frequency synthesis with VCO running to 400MHz and 20Hz frequency resolution for Fin=20MHz, Fout=2-40MHz.  Differential VCO, centre frequency 320MHz. Configurable based on application, including use as standard PLL.  Area 2mm2, Idd=25mA, PN @ 10kHz offset = -100dBc/Hz. Verified by Simulation for XH035.

HT_LDO_HV_GD Driver
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV Gate Driver with HS and LS drive outputs, for internal or external Power MOS drive. Typical load IRFV44VPBF 10V VGS 67nCl. Applications include Half-Bridge operating from 18-28V.  Chargepump required to generate. Area 1.65mm2 including IO, 5mm2 for triple H-bridge. Cross-conduction control, controlled slewrates. Verified by Simulation for XH035.

HT_TSEN Temperature Sensor
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Temperature Sensor -40 to 225°C. Nominal  Accuracy ±5 deg within -20C to 200C, and ±10deg outside this range. Vdd=3.3V, Idd=2mA. Nominal sensitivity=3.5mV/°C. Verified by Simulation for XH035.

HT_LDO_HV_3.3V Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV LDO Vin 18-38V, Vo=3.3V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.

HT_LDO_HV_5V0 Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV LDO Vin 18-38V, Vo=5.0V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.

HT_LDO_HV_12V Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV LDO Vin 18-38V, Vo=12V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.

HT_CP_HV Charge Pumps
Silansys
XA035
MP
Verilog
GDSII

18-28V VDD, 12V Vref, 26-40V Vout Chargepump with 2 external diodes and external Cfly capacitors, for HS gate driving.  Includes programmability of operating freq (nom 4MHz), dead time, slew rate and drive strength.Area 1mm2. Verified by Simulation for XH035.

HT_OpencoreMSP430 Microprocessor
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

High Temperature 200°C OpencoreMSP430 CPU with foundry 3K Data SRAM, 11k Program EEPROM & SRAM IP, 256 byte Data EEPROM, UART, SPI, LIN, GPIO peripherals, Timers, SCAN test. 3.3V, 4MHz operation. Opencore revision 175, 30-Jan-2013. Verified by Simulation for XH035.

VREG1_8 Voltage Regulator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.

XTAL5M Oscillator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic

Low power crystal oscillator for resonator with fast start-up, available for XC018/XH018 MOS3LP, including pads, different pads on request.

TI-RF-CMP Comparators
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-CMP is a low power CMOS RF comparator with 4 ns propagation delay and latch function. ESD protection provided.

TI-RF-DRV Driver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-DRV is a fully differential RF driver for differential signal processing applications. Common-mode level of differential outputs is adjustable that allows to shift easily the input signals for driving single-supply ADCs. ESD protection provided.

TI-RF-MUX Multiplexer
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-RF-MUX is a 4-to-1 RF multiplexer designed with an internal current feedback output amplifier whose gain can be adjusted externally. There is a possibility of optional usage of two 4-to-1 devices as one 8-to-1 multiplexer. ESD protection provided.

TI-RF-Switch Analogue Switches
Thesys-Intechna
0.35 μm
XH035
VS
GDSII
Schematic

The TI-RF-Switch is a broad-band dual SPDT analog switch containing two single-pole double-throw switches. Used CMOS technology provides high isolation and low insertion loss at frequencies up to 1 GHz.

TI-16PI/150M ADC
Thesys-Intechna
0.18 μm
XT018
VS
GDSII
Schematic

TI-16PI/150M is a dual-channel fully differential 16-bit ADC with pipelined architecture optimized for high dynamic performance at sample rates up to 180 MSPS.

TI-Manchester Transceiver
Thesys-Intechna
0.60 µm
XT06
VS
GDSII
Schematic

TI-Manchester is a dual data bus transceiver designed for receiving CMOS/TTL Manchester II data, converting it and transmitting through a stepup transformer to the data bus...

TI-L500 Voltage Regulator
Thesys-Intechna
0.60 µm
XC06
PT
GDSII
Schematic

TI-L500 is a micro-power low dropout linear voltage regulator with fixed 5 V output voltage and input voltage of up to 40 V. ESD protection provided.

TI-DR-H&LS Driver
Thesys-Intechna
1.00 µm
XDH10
VS
Schematic

The driver is a high-voltage device, manufactured with SOI technology. It has a driver structure that enables ti drive independent referenced channel power MOS or IGBT. The upper (floating) section is enabled to work with voltage rail up to 600 V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.

TI-DR-LS Driver
Thesys-Intechna
0.60 µm
XT06
VS
Schematic

The dual high-speed gate drivers are especially well suited  for driving the MOSFETs and IGBTs. Each of the two outputs can sourse and sink 4A of current while producing voltage rise and fall times of less than 10 ns. Low propagation delay and fast, matched rise and fall times make the driver ideal for high-frequency and high-power applications.

aopac01 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. aopac01 is an internally compensated general purpose OpAmp with P-MOS input and common-source output stage.

aopac02 Operational Amplifier
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. aopac02 is an internally compensated rail-to-rail input/output OpAmp.

 


MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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