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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
D17IP15 Voltage Regulator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic

D17IP15 is a voltage regulator with built in reference.  Has 5V low drop out regulator that can operate from 5.5V - 25V supply.  Has 14V regulator when the supply is > 25V.  Can be paired with D17IP16 to generate a voltage oscillator.

D17IP16 Oscillator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic

D17IP16 is a voltage oscillator at 500 kHz.  It requires 3 input reference voltages 1.064V, 1.275V and 0.762V.  These voltages can be generated with the D17IP15.  Output is to designed to drive on chip light loads.

S8 Microprocessor
easics NV
All Geometries
All Processes
VS
VHDL
Verilog

S8 processor/microcontroller: This is a tiny, customizable microcontroller core, available in 8-bit data widths for house keeping of mixed-signal ASICs.

TCP Offload Engine Other
easics NV
All Geometries
All Processes
VS
VHDL
Verilog

Easics' TCP Offload Engine (TOE) can be used to offload the TCP/IP stack from the CPU and handle it in ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible.

8b-20 Msps ADC with 4 :1 Mux ADC
EASii IC
0.18 μm
XP018
VS
Layout
Schematic

High Speed 8 bits ADC running at 20 MSps including an analog multiplexer 4:1
Only  2 clock latency
power :22mW
Voltage supply: 3.3V

ADC12b017kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 12bit resolution, 17kSps, 0.5 LSB INL, 12bit ENOB, 50µW power consumption.

ADC12b054kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 12bit resolution, 54kSps, 1.6 LSB INL, 10.5bit ENOB, 370µW power consumption

ADC16b013kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
PT
GDSII
Schematic

Cyclic single ADC, 16bit resolution, 13kSps, 12.7 bit ENOB, 50µW power consumption

ADC12b020MS350nm ADC
Fraunhofer IIS/EAS
0.35 μm
XH035
PT
GDSII
Schematic

Pipelined ADC, 12bit resolution, 20MSps, 9.6 bit ENOB@2MSps, 9.2 bit ENOB@20MSps,  2 LSB INL, 125mW power consumption

ADC12b040MS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XC018
MP
GDSII
Schematic

Pipeline ADC, 12bit resolution, 1-40MSps, single-end and fully differential input buffer.

ADC15b008kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
MP
GDSII
Schematic

Sigma-Delta-ADC, 15bit, 8-192kS/s sampling rate, up to 4 differential inputs

ADC15b008kS180nm ADC
Fraunhofer IIS/EAS
0.18 μm
XH018
MP
GDSII
Schematic

Sigma-Delta-ADC, 15bit, 8-192kS/s sampling rate, up to 4 differential inputs

PGA180nm AFE Amplifier
Fraunhofer IIS/EAS
0.18 μm
XC018
PT
Schematic
GDSII

Programmable Gain Amplifier, Gain settings 0.5 – 128 (9 steps), (optional) 8-to-1 input mux, (optional) internal chopper stabilizer, temp range from -40 to 175°C

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

DC-DC Converter DC/DC Converters
Ridgetop Group
0.60 µm
XC06
ID
GDSII

Ultra high efficiency programmable output voltage over wide input voltage range, buck/boost. Input: 1.5V - 15V. Output 2V-6V

Comparator 0.6u Comparators
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Ultra Low Power, Wide Supply Range, CMOS

BGR 0.6u Bandgaps
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS

PWM Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

250kHz PWM for DC-DC converters

High V Input Cell Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

High Voltage Input for input voltages up to 100V

Active Shield Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Attacks against digital circuits can be performed by directly tampering with the device's internal structure. Active Shield technology is designed to deter such intrusive attacks by placing a mesh over the sensitive parts of the circuit and monitor

CyberCPU Security
Secure-IC
All Geometries
All Processes
PT
GDSII

CyberCPU comprises technologies for detecting cyber-attacks targeted to hijack and take the control of the CPU. CyberCPU technologies are available as portable security features to be integrated in a targeted CPU architecture or as a ready to use IP Core.

Digital Sensor Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Cryptography attack can inject one or several faults into a device disrupting its functional behavior. The Digital Sensor detect various threats belonging to the family of Fault Injection Attacks (FIA) : Input clock frequency, Input Voltage, Temperature,

PUF Security
Secure-IC
All Geometries
All Processes
PT
GDSII

PUF IP Core is a secret key generation system based on Physically Unclonable Functions (PUF). This feature allows a real protection against the reverse-engineering techniques compared to traditional methods that store the key in non-volatile memory.

Scrambled Bus Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Scrambled Bus IP masks all data carried on the bus with random variables generated locally by cryptographic primitives. Features:
• On-the-fly masking and unmasking, no additional latency
• Transparent for bus masters and slaves
• etc.

Secure Boot Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Provides a secure root-of-trust with a high level of resistance against malevolent attacks, ensures integrity of the SoC security features and guarantees that the firmware is genuine. Optionally, it ensures the firmware’s confidentiality

Secure Clock Security
Secure-IC
All Geometries
All Processes
PT
GDSII

Secure Clock IP core is intended to clock feed all desired hardware, creating a secure clock domain within the System on Chip host. ...it also fuzzes the relevant fault injection moment used by fault injection attacks.

 


MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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