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Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
IPMS_430 Microprocessor
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_16CXX Microprocessor
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

S8 Microprocessor
easics NV
All Geometries
All Processes
VS
VHDL
Verilog

S8 processor/microcontroller: This is a tiny, customizable microcontroller core, available in 8-bit data widths for house keeping of mixed-signal ASICs.

TCP Offload Engine Other
easics NV
All Geometries
All Processes
VS
VHDL
Verilog

Easics' TCP Offload Engine (TOE) can be used to offload the TCP/IP stack from the CPU and handle it in ASIC hardware. This core is an all-hardware configurable IP block. It acts as a TCP server for sending and receiving of TCP/IP data. Because everything is handled in hardware very high throughput and low latency are possible.

BIAS Bias
X-FAB
0.60 µm
XB06
PT
Verilog
Schematic
Layout
Analog Library

XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer

MR74039 Other
Moortec Semiconductor Ltd
0.35 μm
XH035
ID
GDSII
Verilog

The MR74039 is a fully integrated temperature sensor with a 12 Bit digital output designed in the XFab 0.35um XH035 process. It utilises a 12 bit Sigma Delta ADC for increased precision (0.25ºC). The temperature measurement range is fr

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

CM1112ae Voltage Regulator
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.

CM1412ae Power On/Off Reset
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

2Low consumption Power-On Reset (POR) core. The core has a voltage sense (configurable 0.9V - 5.5V), an internal current bias circuit and two configurable assertion delays (default are > 1μs and > 20μs). A configurable hysteresis (default 100mV).

CM1511ae Other
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

Low consumption combo voltage and current reference core. The circuit generates an unbuffered 1.29V, temperature compensated voltage reference (70ppm/°C) and provides a 1.6μA PMOS current branch (200ppm/°C).

CM2013ae ADC
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

Low power, general purpose, 10-bit, 50kSPS, Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) core. The circuit uses one 3.3V analog supply and one 3.3V digital supply and is targeted for microcontroller applications.

CM4013ae Oscillator
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist

General purpose, low power internal oscillator core, 12MHz. The circuit has internal level shifting and start-up circuits. A 4-bit digital bus allows frequency calibration against process variations. Current consumption <40μA, supply voltage 2.7V-3.6V

CM6011ae Other
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

General purpose capacitive sensor core. The circuit is intended for touch sensing applications for use in microcontrollers and has two multiplexed inputs. 3pF input sensibility and output frequency of 460kHz - 600kHz.

CM6111ae Other
chipus
0.35 μm
XH035
PT
GDSII
Verilog
LVS Netlist

30V/20mA Power Driver/Switch - Two modes of operation: switch or programmable current output; short-circuit protection, over-current detection.

HT_MUX_16:1 Multiplexer
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

High Temperature Analog Mux with >50dB isolation and Ron=, Area=0.1mm2, 1dB Compression Current 2mA, Off Isolation Rejection 60dB, Insertion Loss 0.5dB. Verified by Simulation for XH035.  

HT_CSC Current Sensor
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Programmable Trip Current Sense Instrumentation Amp and Comparator.  Differential input assumes 0.01Ω sense resistor. Gain prog of 19x or 38x. FSR=50mV/100mV. Trip Voltage 40/60/90 mV. Latched comparator o/p. Verified by Simulation for XH035.

HT_HRM Other
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Harmonic Reject Mix, Idd=10mA, Area=1mm2, Gain 12dB, 1dB Compression =2Vpp.  Can be simplified (reduce area & power) or simply configured as standard Mixer. Verified by Simulation for XH035.

HT_OSC_8M Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

-40°C-> 220°C Integrated Oscillator Clock Generator, Nominal 8MHz, Vdd=3.3V, Idd=1mA, Variation over supply & temp <5%, 8b DAC for process trim to <1%. Requires low tempco reference current (IP Available). Verified by Simulation for XH035.

HT_PGA Other
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

IF Programmable Gain Amp, Gain Range 6->24dB, Gain Step 6dB, B/W 240kHz, 1dB Compression 5Vpp, Idd=2mA, Area=2mm2. Verified by Simulation for XH035.

HT_LNA_TIA LNA
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Low Noise Transimpedance Amplifier/LNA,Transimpedance 900Ω/3.6kΩ, 1dB Compression 400mVpp, Idd=10mA, Area=1mm2. Verified by Simulation for XH035.

HT_Frac_PLL PLL
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Fractional_N PLL developed for low-noise fractional frequency synthesis with VCO running to 400MHz and 20Hz frequency resolution for Fin=20MHz, Fout=2-40MHz.  Differential VCO, centre frequency 320MHz. Configurable based on application, including use as standard PLL.  Area 2mm2, Idd=25mA, PN @ 10kHz offset = -100dBc/Hz. Verified by Simulation for XH035.

HT_LDO_HV_GD Driver
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV Gate Driver with HS and LS drive outputs, for internal or external Power MOS drive. Typical load IRFV44VPBF 10V VGS 67nCl. Applications include Half-Bridge operating from 18-28V.  Chargepump required to generate. Area 1.65mm2 including IO, 5mm2 for triple H-bridge. Cross-conduction control, controlled slewrates. Verified by Simulation for XH035.

HT_TSEN Temperature Sensor
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

Temperature Sensor -40 to 225°C. Nominal  Accuracy ±5 deg within -20C to 200C, and ±10deg outside this range. Vdd=3.3V, Idd=2mA. Nominal sensitivity=3.5mV/°C. Verified by Simulation for XH035.

HT_LDO_HV_3.3V Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV LDO Vin 18-38V, Vo=3.3V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.

HT_LDO_HV_5V0 Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV LDO Vin 18-38V, Vo=5.0V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.

HT_LDO_HV_12V Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

HV LDO Vin 18-38V, Vo=12V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.

HT_CP_HV Charge Pumps
Silansys
XA035
MP
Verilog
GDSII

18-28V VDD, 12V Vref, 26-40V Vout Chargepump with 2 external diodes and external Cfly capacitors, for HS gate driving.  Includes programmability of operating freq (nom 4MHz), dead time, slew rate and drive strength.Area 1mm2. Verified by Simulation for XH035.

HT_OpencoreMSP430 Microprocessor
Silansys
0.35 μm
XA035
MP
Verilog
GDSII

High Temperature 200°C OpencoreMSP430 CPU with foundry 3K Data SRAM, 11k Program EEPROM & SRAM IP, 256 byte Data EEPROM, UART, SPI, LIN, GPIO peripherals, Timers, SCAN test. 3.3V, 4MHz operation. Opencore revision 175, 30-Jan-2013. Verified by Simulation for XH035.

 


MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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