aregc01
Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aregc01 is a 5V / 3.3V positive voltage linear regulator for up to 10 mA load current.
aregc02
Voltage Regulator
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library
XC10: A_CELLS; A_CELLS_M1. aregc02 is a 2.4V / 3.3V positive voltage switching regulator for on-chip loads and up to 10 mA load current.
aregc01
Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library
XH035: A_CELLS_HV. For MOS module only. aregc01 is a 5V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered viz its high voltage input.
aregc02
Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library
XH035: A_CELLS_HV. For MOS module only. aregc02 is a 12V/3.3V linear voltage regulator for up to 20mA load current. The regulator is powered via its high-voltage input.
AV2102 600mA Buck
Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII
DC/DC regulator.
AV2110 600mA Buck
Voltage Regulator
Aivaka
0.60 µm
XC06
PT
GDSII
DC/DC Buck Regulator with 0% to 100% duty cycle.
VREG1_8
Voltage Regulator
Suter IC-Design AG
0.18 μm
XC018
MP
GDSII
Schematic
Low power voltage regulator for 1.8V logic, requires only an external capacitor, available for XC018/XH018 MOS3LP and MOS5LP, different option available on request.
aregc01_3v3
Voltage Regulator
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library
XC01801_3v3 is a 3.3V/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implimented as a macro cell that fits into the core-limited I/O ring.
CM1112ae
Voltage Regulator
chipus
0.35 μm
XH035
MP
GDSII
Verilog
LVS Netlist
General purpose linear voltage regulator. The circuit generates a 3.3V output voltage from an unregulated input voltage ranging from 5V to 30V. It features short circuit protection and 5mA output current capability.
aregc01_3v3
Voltage Regulator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic
XH018 LP3MOS 3.3V aregc01_3v3 is a 3.3v/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implemented as macro cell that fits into the core-limited I/O ring.
TI-L500
Voltage Regulator
Thesys-Intechna
0.60 µm
XC06
PT
GDSII
Schematic
TI-L500 is a micro-power low dropout linear voltage regulator with fixed 5 V output voltage and input voltage of up to 40 V. ESD protection provided.
D17IP15
Voltage Regulator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic
D17IP15 is a voltage regulator with built in reference. Has 5V low drop out regulator that can operate from 5.5V - 25V supply. Has 14V regulator when the supply is > 25V. Can be paired with D17IP16 to generate a voltage oscillator.
aregc04
Voltage Regulator
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library
XH035: A_CELLS_HV. For MOS module only. aregc04 is a 5V/3.3V linear voltage regulator for up to 5mA load current and internal bandgap reference.
aregc01_5v
Voltage Regulator
X-FAB
0.18 μm
XP018
PT
Schematic
Layout
Analog Library
XP018 LP5MOS/MOS5 aregc01_5v is a 5V/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference.
aregc01_3v3
Voltage Regulator
X-FAB
0.18 μm
XS018
PT
Schematic
Layout
Analog Library
XS018 MOS3LP aregc01_3v3 is a 3.3V/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference.
avrfc01_1v8
Voltage Regulator
X-FAB
0.18 μm
XT018
PT
Schematic
Layout
Analog Library
XT018 LP5MOS avrfc01_1v8 is a general purpose 925mV voltage referrence cell.
aregc01_5v
Voltage Regulator
X-FAB
0.18 μm
XT018
PT
Schematic
Layout
Analog Library
XT018 LP5MOS/MOS5 aregc01_5v is a 5V/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference.
aregc03_5v
Voltage Regulator
X-FAB
0.18 μm
XT018
PT
Schematic
Layout
Analog Library
XT018 LP5MOS/MOS5 aregc03_5v is a linear voltage regulator for in-chip loads to power digital circuitry running at 1.8V.
xpslstc01_5V
Voltage Regulator
X-FAB
0.35 μm
XU035
PT
Schematic
Layout
Analog Library
XU035: XSMPS_CELLS. Xpslstc01_5V is an application specific, 12V to 5V auxiliary internal linear voltage regulator for up to 6mA load current.
HT_OSC_8M
Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII
-40°C-> 220°C Integrated Oscillator Clock Generator, Nominal 8MHz, Vdd=3.3V, Idd=1mA, Variation over supply & temp <5%, 8b DAC for process trim to <1%. Requires low tempco reference current (IP Available). Verified by Simulation for XH035.
HT_LDO_HV_3.3V
Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII
HV LDO Vin 18-38V, Vo=3.3V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.
HT_LDO_HV_5V0
Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII
HV LDO Vin 18-38V, Vo=5.0V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.
HT_LDO_HV_12V
Voltage Regulator
Silansys
0.35 μm
XA035
MP
Verilog
GDSII
HV LDO Vin 18-38V, Vo=12V, Trim in 5% steps, Idd=1mA, Load Current 20mA max, 30dB PSRR, External Decoupling Cap. Verified by Simulation for XH035.
D17IP01
Voltage Driver
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic
D17IP01 is a low power digital pad driver and input, with both and out and input enabled. Operating supply voltage of 2V to 3.6V; maximum delay time of 150ns; static current is leakage; 20ns max rise/fall time for 2pF load.
D17IP13
Voltage Driver
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic
D17IP013D17IP13 is a video amplifier designed to drive 75 ohm coaxial cable. It is configured in the inverting mode and allows minimal distortion for input signals up to 1Vp-p. The output can be muted, gained or attenuated.
LCVCO2
VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library
XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D
LCVCO3
VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library
XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other
RINGVCO1
VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library
XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i
avcoc01_3v3
VCO
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library
XC018 LP 3.3V avcoc01_3v3 is a voltage controlled oscillator (VCO).
D17IP07
Under Voltage Detector
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic
D17IP07 is an under voltage detector. It has an enable signal to allow for detect control. It is designed to output an active low signal when the supply voltage drops below 2V for longer than 1 ms.