IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
abiac03_3v3 Bias
X-FAB
0.18 μm
XS018
MP
Schematic
Layout
Analog Library

XS018 MOS3LP abiac03_3v3 is a general purpose bias cell. The circuit force a current of 10µA to flow through PMOS with W/L ratio of 2*12µm/2µm and NMOS with W/L ratio of 14µm/6µm.

abiac04 Bias
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Abiac04 is a general purpose bias cell. It forces a current of 10µA to flow through PMOS with W/L ratio of 12µm/4µm and NMOS with W/L ratio of 12µm/6µm.

abiac04 Bias
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Abiac04 is a general purpose bias cell. It forces a current of 10µA to flow through PMOS with W/L ratio of 12µm/4µm and NMOS with W/L ratio of 12µm/6µm.

abiac04 Bias
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: A_CELLS_HV. For MOS module only. abiac04 is a high voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through PHV with W/L ratio of 8µm/12µm and NHV with W/L ratio of 8µm/14µm.

abiac05 Bias
X-FAB
0.60 µm
XT06
PT
Schematic
Layout
Analog Library

XT06 abiac05 is a general purpose VTH - based bias cell, a cheaper substitute for abiac02. The circuit forces a current of 2µA (approx.) to flow through P- or N- MOS with W/L ratio of 10µm/10µm.

abiac05 Bias
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. abiac05 is a general purpose VTH-based bias cell. It forces a current of apprx. 2µA through P- or N-MOS with W/L ratio of 10µm/10µm.

abiac06 Bias
X-FAB
0.60 µm
XT06
PT
Schematic
Layout
Analog Library

XT06 abiac06 is a general purpose VTH - based bias cell, a cheaper substitute for abiac03. The circuit forces a current of 10µA (approx.) to flow through P- or N- MOS with W/L ration of 10µm/6µm.

abiac06 Bias
X-FAB
0.60 µm
XC06
PT
Layout
Schematic
Analog Library

XC06: A_CELLS. abiac06 is a general purpose VTH-based bias cell. It forces a current of apprx. 10µA through P- or N-MOS with W/L ratio of 10µm/6µm.

abiac06 Bias
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Abiac06 is a general purpose bias cell. It forces a current of 200nA to flow through PMOS with W/L ratio of 10µm/12µm and NMOS with W/L ratio of 8µm/20µm.

abiac06 Bias
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Abiac06 is a general purpose bias cell. It forces a current of 200nA to flow through PMOS with W/L ratio of 10µm/12µm and NMOS with W/L ratio of 8µm/20µm.

abiac06_1v8 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 1.8V abiac06_1v8 is a general purpose low voltage (down to 1.2V) bias cell with low sensitivity to supply voltage changes. The circuit forces a current of approx 2µA to flow through n-MOS with W/L ration of 20µm/8µm.

abiac06_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LPMOS 1.8V abiac06_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 2µA (approx.) to flow through N-MOS with W/L ratio of 20µm/8µm.

abiac06_1v8 Bias
X-FAB
0.18 μm
XS018
PT
Schematic
Layout
Analog Library

XS018 MOS3LP abiac06_1v8 is a general purpose low voltage (down to 1.2V) VTH-based bias cell.

abiac06_5v Bias
X-FAB
0.18 μm
XC018
PT
Schematic
Layout
Analog Library

XC018 LP 5V abiac06_5v is a general purpose bias cell. The circuit forces a current of 10µA (approx.) to flow through PMOS with W/L ratio of 24µm/3µm and NMOS with W/L ratio of 10µm/4µm.

abiac07 Bias
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. abiac07 is a high-voltage bias cell. The circuit forces a current of 2µA (approx.) to flow through pghv PMOS with W/L ratio of 10µm/10µm and nmv NMOS with W/L ratio of 10µm/12µm.

abiac07_5v Bias
X-FAB
0.18 μm
XC018
PT
Schematic
Layout
Analog Library

XC018 LP 5V abiac07_5v is a general purpose bias cell. The circuit forces a current of 2µA (approx.) to flow through PMOS with W/L ratio of 10µm/6µm and NMOS with W/L ratio of 10µm/12µm.

abiac08 Bias
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS_HV. abiac08 is a high-voltage bias cell. THe circuit forces a current of 2µA (approx.) to flow through pgmv PMOS with W/L ratio of 10µm/10µm and nhv NMOS with W/L ratio od 10µm/12µm. The cell features low-cost process option and is a co

abiac08_1v8 Bias
X-FAB
0.18 μm
XC018
PT
Layout
Schematic
Analog Library

XC018 LP 1.8V abiac08_1v8 is a general purpose low voltage (down to 1.2V) bias cell with low sensitivity to supply voltage changes. The circuit forces a current of approx 10µA to flow through n-MOS with W/L ration of 40µm/6µm.

abiac08_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LPMOS 1.8Vabiac08_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 10µA (approx.) to flow through N-MOS with W/L ratio of 40µm/60µm.

abiac09_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

XH018 LPMOS 1.8V abiac09_1v8 is a general purpose low voltage (down to 1.2V) VTH-based cell.

abiac10_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

XH018 LPMOS 1.8V abiac10_1v8 is a general purpose low voltage (down to 1.2V) VTH-based cell with positive temperature coefficient.

abiac11_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

XH018 LPMOS 1.8V abiac11_1v8 is a general purpose low voltage (down to 1.2V) VTH-based cell.

abiac12_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

XH018 LPMOS 1.8V abiac12_1v8 is a general purpose low voltage (down to 1.2V) VTH-based cell with positive temperature coefficient.

achpc01 Charge Pumps
X-FAB
0.60 µm
XT06
PT
Schematic
Layout
Analog Library

XT06 achpc01 is a doubling charge pump 3.3V => 5.6V.

achpc01 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. achpc01 is doubling charge pump 5V to 8.75V.

achpc01 Charge Pumps
X-FAB
0.60 µm
XC06
PT
Schematic
Layout
Analog Library

XC06: A_CELLS. achpc01 is a doubling charge pump 3.3V -> 5.7V. All capacitors are internal.

achpc02 Charge Pumps
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. achpc02 is a 4-stage Dickson charge pump originally designed for EEPROM.

acmpc01 Comparators
X-FAB
0.60 µm
XT06
PT
Schematic
Layout
Analog Library

XT06 acmpc01 is a low-power CMOS comparator with N-MOS input stage.

acmpc01 Comparators
X-FAB
1.00 µm
XC10
PT
Schematic
Layout
Analog Library

XC10: A_CELLS; A_CELLS_M1. acmpc01 is a general purpose voltage comparator with P-MOS input and hysteresis.

acmpc01 Comparators
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Acmpc01 is a compact low-power CMOS comparator with hysteresis. The input stage is PMOS differential pair.

 


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