IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
arcoc03 Oscillator
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Arcoc03 is a robust 100kHz current-balancing RC oscillator with internal R and C. The cell features very low power consumption, low temperature coefficient of clock frequency and small die area.

arcoc04 Oscillator
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Arcoc04 is a 100kHz adjustable current-balancing RC oscillator with internal R and C. The cell features small die area, very low temperature coefficient of clock frequency and moderate power consumption.

aporc01 Power On/Off Reset
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Aporc01 is a dynamic Power-On-Reset circuit. POR signal turns low when the threshold voltage is reached.

aporc02 Power On/Off Reset
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Aporc02 is a Power-On-Reset circuit with hysteresis. POR signal turns low when the threshold voltage is reached.

aporc03 Power On/Off Reset
X-FAB
1.00 µm
XDH10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Aporc03 is a Power-On-Reset circuit with hysteresis. POR signal turns low when the threshold voltage is reached.

TI-DR-H&LS Driver
Thesys-Intechna
1.00 µm
XDH10
VS
Schematic

The driver is a high-voltage device, manufactured with SOI technology. It has a driver structure that enables ti drive independent referenced channel power MOS or IGBT. The upper (floating) section is enabled to work with voltage rail up to 600 V. The Logic Inputs are CMOS/TTL compatible for ease of interfacing with controlling devices.

aopac01 Operational Amplifier
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Aopac01 is a general purpose internally compensated CMOS OpAmp with PMOS input stage and NPN emitter-follower output stage.

abiac02 Bias
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Abiac02 is a general purpose bias cell. It forces a current of 2µA to flow through PMOS with W/L ratio of 10µm/8µm and NMOS with W/L ratio of 10µm/12µm.

abiac04 Bias
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Abiac04 is a general purpose bias cell. It forces a current of 10µA to flow through PMOS with W/L ratio of 12µm/4µm and NMOS with W/L ratio of 12µm/6µm.

abiac06 Bias
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDH10: A_CELLS. Abiac06 is a general purpose bias cell. It forces a current of 200nA to flow through PMOS with W/L ratio of 10µm/12µm and NMOS with W/L ratio of 8µm/20µm.

acsoc02 Current Source
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Acsoc02 is a general purpose current source. It provides a set of four binary-weighted output currents 1, 2, 4, & 8µA.

acmpc01 Comparators
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Acmpc01 is a compact low-power CMOS comparator with hysteresis. The input stage is PMOS differential pair.

acmpc02 Comparators
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Acmpc02 is a compact low-power CMOS comparator with hysteresis. The input stage is NMOS differential pair.

acmpc03 Comparators
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Acmpc03 is a rail-to-rail CMOS comparator.

acmpc04 Comparators
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Acmpc04 is a current-programmable rail-to-rail CMOS voltage comparator. The speed and power consumption of cell are programmed by means of bias current.

aadcc01 ADC
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Aadcc01 is a 10-bit successive approximation Analog-to-Digital converter (ADC). The ADC operates with a single 5V power supply and an external voltage reference.

adacc01 DAC
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Adacc01 is a 10-bit voltage-scaling (potentiomentric) Digital-to-Analog converter (DAC). The cell operates with a single 5V power supply & external reference voltage.

adacc02 DAC
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Adacc02 is a 8-bit R-2R Digital-to-Analog converter (DAC). The cell operates with a single 5V power supply & external reference voltage.

adacc03 DAC
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Adacc02 is a 10-bit R-2R Digital-to-Analog converter (DAC). The cell operates with a single 5V power supply & external reference voltage.

arcoc01 Oscillator
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Arcoc01 is a robust 1MHz current-balancing RC oscillator with internal R and C. The cell features small die area, very low temperature coefficient of clock frequency and moderate power consumption.

arcoc02 Oscillator
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Arcoc02 is a 1MHz adjustable current-balancing RC oscillator with internal R and C. The cell features small die area, very low temperature coefficient of clock frequency and moderate power consumption.

arcoc03 Oscillator
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Arcoc03 is a robust 100kHz current-balancing RC oscillator with internal R and C. The cell features very low power consumption, low temperature coefficient of clock frequency and small die area.

arcoc04 Oscillator
X-FAB
1.00 µm
XDM10
PT
Schematic
Analog Library
Layout

XDM10: A_CELLS. Arcoc04 is a 100kHz adjustable current-balancing RC oscillator with internal R and C. The cell features small die area, very low temperature coefficient of clock frequency and moderate power consumption.

aporc01 Power On/Off Reset
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Aporc01 is a dynamic Power-On-Reset circuit. POR signal turns low when the threshold voltage is reached.

aporc02 Power On/Off Reset
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Aporc02 is a Power-On-Reset circuit with hysteresis. POR signal turns low when the threshold voltage is reached.

aporc03 Power On/Off Reset
X-FAB
1.00 µm
XDM10
PT
Schematic
Layout
Analog Library

XDM10: A_CELLS. Aporc03 is a Power-On-Reset circuit with hysteresis. POR signal turns low when the threshold voltage is reached.

abgpc01_1v8 Bandgaps
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

 XH018 LPMOS 1.8V abgpc01_1v8 is a general purpose 1.2V bandgap reference with N-well resistirs and PNP (qpvc) diode matrix

abgpc05_1v8 Bandgaps
X-FAB
0.18 μm
XH018
PT
Layout
Schematic
Analog Library

XH018 LPMOS 1.8V abgpc05_1v8 is a general purpose 1.2V bandgap reference with N-well resistors and NPN (qnva) diode matrix.

abiac06_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LPMOS 1.8V abiac06_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 2µA (approx.) to flow through N-MOS with W/L ratio of 20µm/8µm.

abiac08_1v8 Bias
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LPMOS 1.8Vabiac08_1v8 is a general purpose low voltage (down to 1.2V) bias cell. The circuit forces a current of 10µA (approx.) to flow through N-MOS with W/L ratio of 40µm/60µm.

 


MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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