IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
D17IP03 Oscillator
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP03 is an RC oscillator with built in current reference.  The design uses mixed TC resistors and matched MOS VT to reduce PVT dependence.  It is designed to run at 800 KHz nominal with a quiescent current of  20uA.

D17IP04 Digital Filter
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP04 is a 3rd order cascade of integrators and comb, or differentiators,(CIC) digital filter.  In converts a single channel digital bit stream into a 16 bit output word with a 256 clock latency.  The design is optimized for area and power.

D17IP05 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP05 is both a current and voltage reference. The current reference uses a negative TC resistor and VBE to reduce the temperature dependence. The output currents are 2µA and a programmable 200nA, 400nA, 800nA, or 1µA, sinking current. 

D17IP06 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP06 is a digitally configurable current and voltage generator.  The reference includes a temperature compensated current and voltage source.  Output of the amplifiers can drive capacitive modes and settle with 16 bit accuracy within 500ns.

D17IP07 Under Voltage Detector
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP07 is an under voltage detector.  It has an enable signal to allow for detect control. It is designed to output an active low signal when the supply voltage drops below 2V for longer than 1 ms.

D17IP08 Interface
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP08 is a configurable 32 channel sample and hold input interface.  The input connects to a 8pF capacitor to ground through a selection multiplexer.  It can be configured as a daisy chain sample and hold circuit for delay line operations.

D17IP09 Transimpedance Amplifier
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP09 is an 8 channel bank of transimpedance amplifiers.  It has a programmable transimpedance gain.  It is internally compensated and supplies a virtual ground to both sink and source current at the input.

D17IP10 Oscillator
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP10 is a programmable RC oscillator with temperature compensated self bias.  The oscillator has 4 bit of input trim range to account for +/- 20% PVT variation.  The bas frequency of the oscillator is 1.6MHz. 

D17IP11 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP11 is both a current and voltage reference with trimming capability.  The current reference uses a negative TC resistor and VBE to reduce the temperature dependence.  The output currents are 2µA and 1µA x2.

D17IP12 Analog Filter
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP12 is a 3rd order analog filter for video applications.  It has the architecture of a Tow-Thomas biquad.  The biquad is design for frequency tunning.  The implementation is an RC continuous time.  The cut off frequency is 6.5 MHz.

D17IP13 Voltage Driver
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP013D17IP13 is a video amplifier designed to drive 75 ohm coaxial cable.  It is configured in the inverting mode and allows minimal distortion for input signals up to 1Vp-p.  The output can be muted, gained or attenuated.

D17IP14 Transceiver
Desert Microtechnology
0.35 μm
XH035
PT
Layout
Schematic

D17IP14 is a low voltage differential signal (LVDS) receiver (RX) for digital video data transfer.  It adherers to LVDS standards.  It has a 400 ohm input impedance. It amplifies the input signals to CMOS levels, 0 to 3.3V. 

LNA1 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA3 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA3 is a low noise amplifier with on-chip inductor. It should be biased by the RF bias cell.

LCVCO2 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

RINGVCO1 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_VCO_CELLS. RINGVCO1 is a fully integrated VCO. It should be biased by the RF bias cell. It consists of a ringoscillator that is tuned by switching the delay chain between 2 and 4 delay stages. The transition between the two borders i

MIXER Mixer
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_MIXER_CELLS. MIXER is a down conversion mixer based on a Gilbert cell topology. It should be biased by the RF bias cell.

PA Power Amplifiers
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_PA_CELLS. PA is a non-linear Power Amplifier that is intended for the transmission of ASK and FSK signals. Its output power level can be digitally controlled in 4 steps. It should be biased by the RF bias cell.

DIV32 Divider
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.

BIAS Bias
X-FAB
0.60 µm
XB06
PT
Verilog
Schematic
Layout
Analog Library

XB06: LNA library: RF_BIAS_CELLS. BIAS is a bias cell intended for use with various RF building blocks. It is designed as a bandgap reference as well as voltage-to-current converter. Current biasing is preferable because of the higher immunity to interfer

OEIC_Fast Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Fast is a fast DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

OEIC_Sensitive Optical Receiver Channel
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. OEIC_Sensitive is a sensitive DVD receiver channel with two selectable gain settings. Can be integrated with photodiode to form a complete optical receiver channel optimized for 660nm wavelengths.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

aopac01 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: A_CELLS. aopac01 is a low power internal frequency-compensated CMOS operational amplifier with pmos input stage

aopac02 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac02 is an internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac03 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac03 is a fast internal frequency-compensated CMOS operational amplifier with p-mos input stage

aopac05 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac05 is a low power internal frequency-compensated CMOS operational amplifier with nmos input stage

aopac06 Operational Amplifier
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. aopac06 is an internal frequency-compensated CMOS operational amplifier with n-mos input stage

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 181 to 210 out of 381

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