IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
aadcc01_3v3 ADC
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aadcc01_3v3 is a 10-bit successive approximation Analog-to-Digital converter. The ADC operates with a single 3.3V analog power supply; 1.8V digital power supply and an external voltage reference.

adacc01_3v3 DAC
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V adacc01_3v3 is a 10-bit voltage-scaling (potentiometric) Digital-to-Analog converter. The adacc01 DAC operates with a single 3.3V analog power supply; a 1.8V digital power supply and an external reference voltage.

aporc02_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit with hysteresis. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

aporc03_3v3 Power on Reset
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aporc02_3v3 is a Power-on-Reset circuit. Reset signal are generated on power-on and power-off transitions. Both high and low (POR and PORB) reset signals are available.

aregc01_3v3 Voltage Regulator
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V aregc01_3v3 is a 3.3v/1.8V linear voltage regulator for up to 20mA load current and internal bandgap reference. The regulator is implemented as macro cell that fits into the core-limited I/O ring.

atmpc01_3v3 Other
X-FAB
0.18 μm
XH018
PT
Analog Library
Layout
Schematic

XH018 LP3MOS 3.3V atmpc01_3v3 is a high-temperature alarm cirsuit. When the chip temperature rises over the high threshold temperature (133°C approx) an OVT (active high) signal is activated.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

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