IP Portal

Sel. IP Name Category Provider Geometry Process Name Status Deliverable Description
D17IP11 Current / Voltage Reference
Desert Microtechnology
0.35 μm
XH035
MP
GDSII
Schematic

D17IP11 is both a current and voltage reference with trimming capability.  The current reference uses a negative TC resistor and VBE to reduce the temperature dependence.  The output currents are 2µA and 1µA x2.

D17IP12 Analog Filter
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP12 is a 3rd order analog filter for video applications.  It has the architecture of a Tow-Thomas biquad.  The biquad is design for frequency tunning.  The implementation is an RC continuous time.  The cut off frequency is 6.5 MHz.

D17IP13 Voltage Driver
Desert Microtechnology
0.35 μm
XH035
PT
GDSII
Schematic

D17IP013D17IP13 is a video amplifier designed to drive 75 ohm coaxial cable.  It is configured in the inverting mode and allows minimal distortion for input signals up to 1Vp-p.  The output can be muted, gained or attenuated.

D17IP14 Transceiver
Desert Microtechnology
0.35 μm
XH035
PT
Layout
Schematic

D17IP14 is a low voltage differential signal (LVDS) receiver (RX) for digital video data transfer.  It adherers to LVDS standards.  It has a 400 ohm input impedance. It amplifies the input signals to CMOS levels, 0 to 3.3V. 

D17IP15 Voltage Regulator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic

D17IP15 is a voltage regulator with built in reference.  Has 5V low drop out regulator that can operate from 5.5V - 25V supply.  Has 14V regulator when the supply is > 25V.  Can be paired with D17IP16 to generate a voltage oscillator.

D17IP16 Oscillator
Desert Microtechnology
1.00 µm
XC10
MP
GDSII
Schematic

D17IP16 is a voltage oscillator at 500 kHz.  It requires 3 input reference voltages 1.064V, 1.275V and 0.762V.  These voltages can be generated with the D17IP15.  Output is to designed to drive on chip light loads.

DAC-7bit-0.6u DAC
Ridgetop Group
0.60 µm
XC06
PT
GDSII

Low Power, Wide Supply Range, CMOS, output to pos rail

dac10 DAC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recomm

DAC10 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC10 is a 10-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the

DAC6rs DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC6rs is a 6-bit digital-to-analog converter. The architecture is based on a resistor divider. The output impedance is code dependent.

dac8 DAC
X-FAB
0.80 µm
CX08
PT
Schematic
Layout
Analog Library

CX08A: Analog library. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommen

DAC8 DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC8 is a 8-bit digital-to-analog converter. The architecture is based on two resistor dividers. Because of its high output impedance, which is also code dependent, a low offset buffer operational amplifier is strictly recommended at the ou

DAC8rs DAC
X-FAB
0.60 µm
XB06
PT
Layout
Schematic
Analog Library

XB06: A_CELLS. DAC8rs is a 8-bit digital-to-analog converter. The architecture is based on a resistor divider. The output impedance is code dependent.

DC-DC Converter DC/DC Converters
Ridgetop Group
0.60 µm
XC06
ID
GDSII

Ultra high efficiency programmable output voltage over wide input voltage range, buck/boost. Input: 1.5V - 15V. Output 2V-6V

DIV32 Divider
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed divider ratio of 32. It should be biased by the RF bias cell.

DIV32 Divider
X-FAB
0.35 μm
XH035
PT
Layout
Schematic
Analog Library

XH035: DIVIDER Library: RF_DIVIDER_CELLS. DIV32 is a Prescaler with a fixed ratio of 32. It should be biased by the RF bias cell.

DPIN Integrated Photodiode
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: OEIC Building Block Library. DPIN_5050 and DPIN_50100 are fast photodiodes with a vertical PIN structure optimized forred light (660nm).

DT2120 ADC
Digian Technology,Inc.
0.35 μm
XH035
MP
GDSII

The dT2120 is designed featuring low-voltage and low-power mono ADC (Analog-to -Digital Converter) for sensor applications. The ADC architecture is using 4th-order 1bit sigma-delta modulator with 64-times oversampling. The dT2120’s in

High V Input Cell Other
Ridgetop Group
0.35 μm
XH035
ID
GDSII

High Voltage Input for input voltages up to 100V

IMMS SENT Transmitter Soft IP
IMMS GmbH
All Geometries
All Processes
PT
Verilog

Silicon-proven Verilog implementation of a flexible configurable SENT transmitter according to SAE standard J2716 JAN2010 “SENT – Single Edge Nibble Transmission for Automotive Applications”. Up to 16-bit data from two independent sensors.

IPMS_16CXX Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

8 Bit Microprocessor. The core IPMS_16CXX is a 8-bit microcontroller compatible to PIC 16CXX-family from Microchip.

IPMS_430 Microprocessor
Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

Compatible in its properties, like instruction set, address space and time behavior with the standard CPU MSP430 from TI. Important features:
- 16 bit Risc CPU
- 7 address modes for source operands
- several low power features

IPMS_CAN_FD Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

IPMS_CAN is a CAN bus controller that performs serial communication according to the CAN 2.0B and the CAN FD specification.It is compatible to ISO CAN FD andthe non-ISO (Bosch) CAN FD standard and has extended time stamp and time trigger capabilities.

IPMS_LIN Soft IP
Fraunhofer IPMS
All Geometries
All Processes
PT
VHDL
Verilog

LIN (Local Interconnect Network) is a serial communication protocol used in low cost automotive networks. It enables cost efficient bus communication for applications where the bandwidth of CAN is not required. Support of LIN specification 2.2A

LCVCO2 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO2 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It is based on a cross-coupled bipolar transistor pair. It contains AC-coupled varactors and a special circuit technique for maintaining the D

LCVCO3 VCO
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LCVCO_CELLS. LCVCO3 is a fully integrated LC-VCO. It should be biased by the RF bias cell. It contains a cross-coupled bipolar transistor pair and direct coupled varactors. For this reason, it has a higher tuning range than the other

LNA1 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA 1 is a low noise amplifier. It shoud be biased by the RF bias cell.

LNA1 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA1 is a broadband low noise amplifier. It should be bieased by the RF bias cell.

LNA2 LNA
X-FAB
0.60 µm
XB06
PT
Schematic
Layout
Analog Library

XB06: LNA library: RF_LNA_CELLS. LNA2 is a low noise amplifier. It should be biased by the RF bias cell

LNA2 LNA
X-FAB
0.35 μm
XH035
PT
Schematic
Layout
Analog Library

XH035: LNA Library: RF_LNA_CELLS. LNA2 is a narrowband low noise amplifier. It should be biased by the RF bias cell.

 

MP = Mass ProductionPT = Prototyping, Silicon provenID = in DesignVS = Verified by Simulations (Soft-IP)

Displaying results 331 to 360 out of 381

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